2010 NASA/ESA Conference on Adaptive Hardware and Systems最新文献_第2页

Rapid development of space applications with responsive digital electronics board and LabVIEW FPGA 快速发展的空间应用与响应式数字电子板和LabVIEW FPGA

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546278

M. B. McMickell, P. Tanzillo, T. Kreider, Kosta Ilic

引用次数: 7

A fuzzy logic based dynamic reconfiguration scheme for optimal energy and throughput in symmetric chip multiprocessors 一种基于模糊逻辑的对称芯片多处理器能量和吞吐量优化动态重构方案

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546239

Muhammad Yasir Qadri, K. Mcdonald-Maier

{"title":"A fuzzy logic based dynamic reconfiguration scheme for optimal energy and throughput in symmetric chip multiprocessors","authors":"Muhammad Yasir Qadri, K. Mcdonald-Maier","doi":"10.1109/AHS.2010.5546239","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546239","url":null,"abstract":"Embedded systems architectures have traditionally often been investigated and designed in order to achieve a greater throughput combined with minimum energy consumption. With the advent of reconfigurable architectures it is now possible to support algorithms to find optimal solutions for an improved energy and throughput balance. As a result of ongoing research several online and offline techniques and algorithm have been proposed for hardware adaptation. This paper presents a novel coarse-grained reconfigurable symmetric chip multiprocessor (SCMP) architecture managed by a fuzzy logic engine that balances performance and energy consumption. The architecture incorporates reconfigurable level 1 (L1) caches, power gated cores and adaptive on-chip network routers to allow minimizing leakage energy effects for inactive components. A coarse grained architecture was selected as to be a focus for this study as it typically allows for fast reconfiguration as compared to the finegrained architectures, thus making it more feasible to be used for runtime adaption schemes. The presented architecture is analyzed using a set of OpenMP based parallel benchmarks and the results show significant improvements in performance while maintaining minimum energy consumption.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134122118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Wireless intra-spacecraft communication: The benefits and the challenges 宇宙飞船内无线通信:优势与挑战

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546219

W. H. Zheng, John T. Armstrong

引用次数: 34

A formal approach to self-configurable swarm-based space-exploration systems 一种基于自配置群的空间探索系统的形式化方法

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546276

Emil Vassev, M. Hinchey, P. Nixon

引用次数: 7

LabVIEW™: A graphical system design environment for adaptive hardware/software systems LabVIEW™:用于自适应硬件/软件系统的图形系统设计环境

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546280

Guoqiang Wang, H. Andrade

引用次数: 4

Acceleration method of optical reconfigurations using analog configuration contexts 使用模拟配置上下文的光学重构加速方法

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546242

Yuji Aoyama, Minoru Watanabe

引用次数: 1

iBoard: A highly-capable, high-performance, reconfigurable FPGA-based building block for flight instrument digital electronics iBoard:一种高性能、可重构的基于fpga的飞行仪表数字电子构建模块

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546279

Yutao He, M. Ashtijou

引用次数: 6

Use of a multi-objective fitness function to improve cartesian genetic programming circuits 利用多目标适应度函数改进笛卡尔遗传规划电路

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546262

J. Hilder, James Alfred Walker, A. Tyrrell

引用次数: 24

Hardware implementation of the FAPEC lossless data compressor for space 硬件实现的FAPEC无损数据压缩空间

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546264

A. G. Villafranca, S. Mignot, J. Portell, E. García–Berro

{"title":"Hardware implementation of the FAPEC lossless data compressor for space","authors":"A. G. Villafranca, S. Mignot, J. Portell, E. García–Berro","doi":"10.1109/AHS.2010.5546264","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546264","url":null,"abstract":"The instruments used in modern space missions require increasing amounts of telemetry resources to download the acquired data to the ground. Data compression helps to mitigate this problem and, therefore, it is currently seen as a mandatory stage for most of the missions, although the available on-board processing power is often modest. In many cases, data compression must be performed without losses. FAPEC is a lossless data compression algorithm that typically offers better ratios than the CCSDS 121.0 recommendation on realistic data sets. Its compression efficiency is higher than 90% of the Shannon limit in most cases, even in presence of large amounts of noise and outliers. FAPEC has been successfully implemented in software and its low-complexity algorithm also seemed suitable for a hardware implementation. In this paper we describe a prototype FPGA implementation which has been developed targeting the antifuse radiation-hardened RTAX Actel family. We have assessed that FAPEC can be easily implemented in hardware without requiring an external memory. The prototype presents an initial throughput of 32 Mbit/s and a complexity of 120 Kgate, hence being a compact and a robust solution for generic lossless compression. Finally, we discuss potential improvements that could easily boost the performance beyond the barrier of 100 Mbit/s.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129385276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

R3TOS: A reliable reconfigurable real-time operating system R3TOS:可靠的可重构实时操作系统

2010 NASA/ESA Conference on Adaptive Hardware and Systems Pub Date : 2010-06-15 DOI: 10.1109/AHS.2010.5546274

X. Iturbe, K. Benkrid, A. Erdogan, T. Arslan, M. Azkarate-askasua, I. Martinez, A. Perez

引用次数: 39