2010 NASA/ESA Conference on Adaptive Hardware and Systems最新文献

{"title":"An adaptive algorithm for reconfigurable analog-to-digital converters","authors":"Z. Razak, A. Erdogan, T. Arslan","doi":"10.1109/AHS.2010.5546250","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546250","url":null,"abstract":"Wireless portable device is desired to efficiently manage its power consumption in order to prolong its battery life. By dynamic monitoring, power utilization can be adjusted according to different signal behaviors and operation modes. This paper proposes a new adaptive algorithm for reconfigurable analog-to-digital converters (ReADC). Reconfiguration of analog-to-digital converter (ADC) is achieved by exploiting switching activity of its digital outputs and adjusts its resolution via an adaptive digital controller unit. The converter increases its resolution when the digital output changes is high and reduces its resolution when signal variation is low. MATLAB simulation results show that the algorithm is real-time adaptive and suitable for typical converter types implementation. Depending on different signal scenarios, average resolution of ReADC is lower than a fixed operation ADC. As approximation, power model for ReADC is presented to estimate ReADC power consumption especially for pipeline implementation. When implemented as adaptive control unit (ACU) for reconfigurable pipeline ADC, only 40 percent of power is used when operates with minimum 4-bit compared to conventional 10-bit ADC. Over entire signal duration, this power saving approach is capable of saving power up to 50 percent of total ADC power usage.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130170447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An adaptive communications module for on-board computers of satellites","authors":"E. Bezerra, G. M. Almeida, L. Azevedo","doi":"10.1109/AHS.2010.5546240","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546240","url":null,"abstract":"Traditionally, computational systems based on FPGA technology take advantage of the device's configurable resources in order to adapt to different working scenarios. This paper presents a communication system developed in VHDL, targeting an anti-fuse programmable once FPGA device, that adapts to environmental conditions, with no use of reconfigurable technology. The design and implementation of the communications module of the target spacecraft is briefly introduced aiming a better understanding of the proposed approach.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128421303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Error-detecting/correcting-code-based self-checked/corrected/timed circuits","authors":"Bao Liu","doi":"10.1109/AHS.2010.5546217","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546217","url":null,"abstract":"Nanoscale VLSI design faces unprecedented reliability challenges in the presence of prevalent catastrophic defects, soft errors and parametric variations. In this paper, I propose a group of error-detecting/correcting-code(EDC/ECC)-based self-checked/corrected/timed circuits for logic robustness and performance scalability in nanoscale VLSI design. Compared with the existing techniques, the proposed EDC self-checked circuits achieve increased reliability enhancement with comparable hardware overhead, or reduced hardware overhead for the same level of reliability. Simply applying the ECC schemes in memory systems to sequential elements does not achieve reduced hardware overhead for the same level of reliability compared with the existing techniques. EDC self-timed circuits achieve further improved performance scaling with moderately increased hardware overhead, giving a promising nanoscale VLSI circuit paradigm for further scaled technologies.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116117482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and implementation of a radiation tolerant on-board computer for science technology satellite-3","authors":"Dong-Soo Kang, Kyoung-Son Jhang, Dae-Soo Oh","doi":"10.1109/AHS.2010.5546260","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546260","url":null,"abstract":"This paper describes the design and implementation of a radiation tolerant on-board computer (OBC) for the science and technology satellite-3 (STSAT-3). SRAM-based FPGAs are replacing traditional integrated circuits for space applications. However, it is difficult to employ the approach in space applications without radiation tolerant schemes to deal with the radiation effects such as single event upset (SEU). To mitigate the SEU effect, we apply a triple modular redundancy (TMR) scheme to the STSAT-3 OBC based on FPGA. Although there is an overhead in area, power and minimum clock period, we notice through a radiation test in an irradiation facility that our TMR based OBC is immune to the radiation environments up to a proton energy of 20.3MeV. The radiation environment of the test is expected to be more severe than the environment in which STSAT-3 is to be located.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134589701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive phase synchronization in distributed digital arrays","authors":"D. Jenn, Jiheon Ryu, Tsai-Yen Chang, R. Broadston","doi":"10.1109/AHS.2010.5546258","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546258","url":null,"abstract":"Self-synchronizing distributed arrays have been investigated for a number of sensor applications such as radar. This paper discusses several methods for phase synchronizing a distributed array so that coherent processing can be performed. One of the concepts involves transmission of a beacon that is used directly as the frequency reference. After a phase synchronization process is performed sequentially across the array, measured phase differences are obtained that can be used in the digital processing to compensate for hardware and propagation channel differences. The concept was demonstrated for a two element array using commercial hardware at 2.45 GHz. Leakage cancellation techniques were employed to achieve phase accuracies of approximately 20 degrees.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121170813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An adaptable low density parity check (LDPC) engine for space based communication systems","authors":"Gregory M. Striemer, A. Akoglu","doi":"10.1109/AHS.2010.5546275","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546275","url":null,"abstract":"Space communication systems are characterized by the severe limitations to the on-board computational power and the tight constraints of received signal strengths. Also, these systems observe degradation in signals caused by large propagation latencies, extreme distances traveled, as well as data corruption causing high biterror rates. LDPC codes provide powerful error correction capability where signal power is very low, making them an ideal candidate for space based applications. A hardware architecture that is configurable to dynamic changes in channel conditions is a necessity for error resilient communication systems. In this study we demonstrate the feasibility of designing an FPGA based adaptable LDPC decoder architecture that also matches the throughput demand of current space based communications requirements. We design an LDPC engine that is adaptable to three code rates by taking advantage of the partial reconfiguration technology and parallel nature of the FPGA architecture. We evaluate the tradeoff between the level of parallelism to exploit on the FPGA when implementing LDPC codes and resource demand for each code rate under the constraints of delivering a partially reconfigurable and adaptable solution. Based on the implementation using a Xilinx Virtex-5 FPGA, our design handles context switching between the codes on board in 92µs.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115987443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On DESTINY instrument electrical and electronics subsystem framework","authors":"S. Kizhner, D. Benford, T. Lauer","doi":"10.1109/AHS.2010.5546251","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546251","url":null,"abstract":"Future space missions are going to require a few large focal planes with many sensing arrays and hundreds of millions of pixels all read out at high data rates,. This will place unique demands on the electrical and electronics (EE) subsystem design and it will be critically important to have high technology readiness level (TRL) EE concepts ready to support such missions. One such mission is the Joint Dark Energy Mission (JDEM) charged with making precise measurements of expansion rate of the universe to reveal vital clues about the nature of dark energy - a hypothetical form of energy that permeates all of space and tends to increase the rate of expansion. One of three JDEM concept studies - the Dark Energy Space Telescope (DESTINY) was conducted in 2008 at the NASA's Goddard Space Flight Center (GSFC) in Greenbelt, Maryland. This paper presents the EE subsystem framework, which evolved from the DESTINY science instrument study. It describes the main challenges and implementation concepts related to the design of an EE subsystem featuring multiple focal planes populated with dozens of large arrays and millions of pixels. The focal planes are passively cooled to cryogenic temperatures (below 140 K). The sensor mosaic is controlled by a large number of Readout Integrated Circuits and Application Specific Integrated Circuits - the ROICs/ASICs in near proximity to their sensor focal planes. The ASICs, in turn, are serviced by a set of “warm” EE subsystem boxes performing Field Programmable Gate Array (FPGA) based digital signal processing (DSP) computations of complex algorithms, such as sampling-up-the-ramp algorithm (SUTR), over large volumes of fast data streams. The SUTR boxes are supported by the Instrument Control/Command and Data Handling box (ICDH Primary and Backup boxes) for lossless data compression, command and low volume telemetry handling, power conversion and for communications with the spacecraft. This paper outlines how the JDEM DESTINY instrument EE subsystem can be built now, a design that is generally applicable to a wide variety of missions using large focal planes with large mosaics of sensors.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116236357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Balancing exploration and exploitation in an adaptive three-dimensional cellular genetic algorithm via a probabilistic selection operator","authors":"Asmaa Al-Naqi, A. Erdogan, T. Arslan, Y. Mathieu","doi":"10.1109/AHS.2010.5546248","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546248","url":null,"abstract":"Pre-fetching in a memory hierarchy is known to alleviate the “memory wall” paradigm but its use is impeded because of the difficulty to estimate efficiency when used in a complex system such as a SoC (System on Chip) or NoC (Network on Chip). Therefore, some methods are needed to evaluate the benefit of pre-fetching at the earliest possible stage in a design flow to help the designer choose architectural parameters or transform the application algorithm. In this paper we show that the emulation platform implementing the nD-AP Cache (n-Dimensional Adaptive and Predictive Cache) allows to perform a platform-independent measurement of this cache efficiency. The nD-AP Cache performs pre-fetching in multidimensional arrays which are commonly used in image processing and multimedia applications. The obtained metric can be used to extrapolate the cache performance in a much broader system configuration. The method to compute this metric is the calibration process. The performed benchmarks show that the calibration process is confident. Also, we measured that the nD-AP Cache is two times faster than a standard PowerPC 2-way set associative cache in the context of an image processing kernel.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129704101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A very high resolution DAC at 1kHz for space applications","authors":"G. Tsiligiannis, K. Makris, Tasos Lambaounas, D. Fragopoulos, Panagiotis Anagnostopoulos, C. Papadas, J. Schoellkopf, B. Glass","doi":"10.1109/AHS.2010.5546232","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546232","url":null,"abstract":"In this paper a 24-bit Digital to Analog Converter using the ΣΔ modulation suitable for space applications is presented. This converter operates in the frequency range of 0.1 mHz up to 1kHz It features a current steering output stage consisting of 32 differential current sources. The device includes an I2C protocol which allows the selection of the Oversampling, Ratio of the converter to be either x128 or x256 for a 12 kHz or 6 kHz sampling ratio respectively. This circuit can be used either as a stand alone device or embedded into an ASIC as an IP core.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129807551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient analog architectures for DCT processing","authors":"Surya Prakash Noolu, M. Baghini, R. Velmurugan","doi":"10.1109/AHS.2010.5546237","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546237","url":null,"abstract":"This paper presents for the first time full analog design of three different algorithms for 8 × 8 two Dimensional (2-D) Discrete Cosine Transform (DCT), using current-mode analog modules. The operation of each processor is explained with block diagrams and circuit diagrams. All these three structures need no memory. Next, three algorithms which are implemented in analog domain, are compared with respect to the number of transistors and power dissipation. Finally, the architecture with matrix simplification is chosen for simulation as it needs only 2752 transistors and dissipates less power, compared to other two architectures. The entire analog 2-D DCT processor has been implemented and laid out in UMC 0.18- µm technology. The post layout simulation results show that average PSNR is 25.6 dB, maximum power dissipation is 5.67 mW and transform speed is less than 70 nS.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124153290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}