Error-detecting/correcting-code-based self-checked/corrected/timed circuits

Abstract

Nanoscale VLSI design faces unprecedented reliability challenges in the presence of prevalent catastrophic defects, soft errors and parametric variations. In this paper, I propose a group of error-detecting/correcting-code(EDC/ECC)-based self-checked/corrected/timed circuits for logic robustness and performance scalability in nanoscale VLSI design. Compared with the existing techniques, the proposed EDC self-checked circuits achieve increased reliability enhancement with comparable hardware overhead, or reduced hardware overhead for the same level of reliability. Simply applying the ECC schemes in memory systems to sequential elements does not achieve reduced hardware overhead for the same level of reliability compared with the existing techniques. EDC self-timed circuits achieve further improved performance scaling with moderately increased hardware overhead, giving a promising nanoscale VLSI circuit paradigm for further scaled technologies.