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Proceedings. Design Automation Conference最新文献

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Timing analysis of esterel programs on general-purpose multiprocessors 通用多处理机上esterl程序的时序分析
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837288
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, S. Chakraborty
{"title":"Timing analysis of esterel programs on general-purpose multiprocessors","authors":"Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, S. Chakraborty","doi":"10.1145/1837274.1837288","DOIUrl":"https://doi.org/10.1145/1837274.1837288","url":null,"abstract":"Synchronous languages like Esterel have gained wide popularity in certain domains such as avionics. However, platform-specific timing analysis of code generated from Esterel-like specifications have mostly been neglected so far. The growing volume of electronics and software in domains like automotive, calls for formal-specification based code generation to replace manually written and optimized code. Such cost-sensitive domains require tight estimation of timing properties of the generated code. Towards this goal, we propose a scheme for generating C code from Esterel specifications for a multiprocessor platform, followed by timing analysis of the generated code. Due to dependencies across program fragments mapped onto different processors, traditional Worst-Case Execution Time (WCET) analysis techniques for sequential programs cannot applied be to this setting. Our proposed timing analysis technique is tailored to capture such inter-processor code dependencies. Our main novelty stems from how we detect and remove infeasible paths arising from a multiprocessor implementation during our timing analysis. We apply our timing analysis on a number of standard Esterel benchmarks, which show that performing the proposed inter-processor infeasible path elimination may lead to up to 14.3% tighter estimation of the WCRT, thereby leading to resource over-dimensioning and poor design.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"1 1","pages":"48-51"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76346578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances 生成嵌入产量的Pareto-front，以同时优化产量和性能
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837502
Yu Liu, M. Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa
{"title":"Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances","authors":"Yu Liu, M. Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa","doi":"10.1145/1837274.1837502","DOIUrl":"https://doi.org/10.1145/1837274.1837502","url":null,"abstract":"As the variations of shrunk processes increasing at rapid rate, the performances of analog/mixed-signal chips remarkably fluctuate. It is necessary to take the yield as a design objective in design optimization. This paper presents a novel method to generate yield-embedded Pareto-front to simultaneously optimize both the yield and performances. Unlike the traditional approaches which generate the yield-aware Pareto-front to optimize performances for the fixed yield, this work embeds the yield as an objective of the optimization and evolutionarily optimizes both yield and performances by the so-called yield-embedded NSGA. The experiments demonstrate the gradual evolutions and global searching for the better performances and higher yields under PVT variations. The generation accelerated by parallel computations gains 4.8x speedup with 80% efficiency.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"1 1","pages":"909-912"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83097016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
BLoG: Post-Silicon bug localization in processors using bug localization graphs 博客:在处理器中使用bug定位图进行后硅bug定位
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837367
Sung-Boem Park, Anne Bracy, Hong Wang, S. Mitra
{"title":"BLoG: Post-Silicon bug localization in processors using bug localization graphs","authors":"Sung-Boem Park, Anne Bracy, Hong Wang, S. Mitra","doi":"10.1145/1837274.1837367","DOIUrl":"https://doi.org/10.1145/1837274.1837367","url":null,"abstract":"Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"1 1","pages":"368-373"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91285214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Lattice-based computation of boolean functions 基于格的布尔函数计算
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837423
M. Altun, Marc D. Riedel
{"title":"Lattice-based computation of boolean functions","authors":"M. Altun, Marc D. Riedel","doi":"10.1145/1837274.1837423","DOIUrl":"https://doi.org/10.1145/1837274.1837423","url":null,"abstract":"This paper studies the implementation of Boolean functions with lattices of two-dimensional switches. Each switch is controlled by a Boolean literal. If the literal is 1, the switch is connected to its four neighbours; else it is not connected. Boolean functions are implemented in terms of connectivity across the lattice: a Boolean function evaluates to 1 iff there exists a top-to-bottom path. The paper addresses the following synthesis problem: how should we map literals to switches in a lattice in order to implement a given target Boolean function? We seek to minimize the number of switches. Also, we aim for an efficient algorithm - one that does not exhaustively enumerate paths. We exploit the concept of lattice and Boolean function duality. We demonstrate a synthesis method that produces lattices with a number of switches that grows linearly with the number of product terms in the function. Our algorithm runs in time that grows polynomially.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"40 1","pages":"609-612"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85118564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
On the costs and benefits of stochasticity in stream processing 论流处理中随机性的成本与收益
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837357
R. Nadakuditi, I. Markov
{"title":"On the costs and benefits of stochasticity in stream processing","authors":"R. Nadakuditi, I. Markov","doi":"10.1145/1837274.1837357","DOIUrl":"https://doi.org/10.1145/1837274.1837357","url":null,"abstract":"With the end of clock-frequency scaling, parallelism has emerged as the key driver of chip-performance growth. Yet, several factors undermine efficient simultaneous use of on-chip resources, which continue scaling with Moore's law. These factors are often due to sequential dependencies, as illustrated by Amdahl's law. Quantifying achievable parallelism can help prevent futile programming efforts and guide innovation toward the most significant challenges. To complement Amdahl's law, we focus on stream processing and quantify performance losses due to stochastic runtimes. Using spectral theory of random matrices, we derive new analytical results and validate them by numerical simulations. These results allow us to explore unique benefits of stochasticity and show that they outweigh the costs for software streams.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"49 1","pages":"320-325"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85363574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Does IC design have a future in the clouds? IC设计在云端有未来吗?
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837377
A. Kuehlmann, R. Camposano, James Colgan, J. Chilton, Samuel George, Rean Griffith, Paul Leventis, Deepak Singh
{"title":"Does IC design have a future in the clouds?","authors":"A. Kuehlmann, R. Camposano, James Colgan, J. Chilton, Samuel George, Rean Griffith, Paul Leventis, Deepak Singh","doi":"10.1145/1837274.1837377","DOIUrl":"https://doi.org/10.1145/1837274.1837377","url":null,"abstract":"Cloud computing is used to describe a collection of (remote) data centers (the hardware and the software) and applications delivered from them as a service (SaaS, Software as a Service). Its success is driven by the cost-effective on-demand availability of large, scalable amounts of computing resources. The cloud has become an established paradigm for many enterprise and consumer applications such as email, web servers, productivity applications, customer relationship management, etc. However, in IC design its success is still limited.This panel will discuss the real and perceived hurdles that currently prevent a broad adoption of cloud computing in IC design, and several scenarios on how this could happen.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"84 1","pages":"412-414"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83941520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation 考虑弱空间相关性的全芯片统计泄漏功率线性分析算法
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837394
Ruijing Shen, S. Tan, Jinjun Xiong
{"title":"A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation","authors":"Ruijing Shen, S. Tan, Jinjun Xiong","doi":"10.1145/1837274.1837394","DOIUrl":"https://doi.org/10.1145/1837274.1837394","url":null,"abstract":"Full-chip statistical leakage power analysis typically requires quadratic time complexity in the presence of spatial correlation. When spatial correlation are strong (with large spatial correlation length), efficient linear time complexity analysis can be attained as the number of variational variables can be significantly reduced. However this is not the case for circuits where gate leakage currents are weakly correlated. In this paper, we present a linear time algorithm for statistical leakage power analysis in the presence of weak spatial correlation. The new algorithm exploits the fact that gate leakage current can be efficiently computed locally when correlation is weak. We adopt a newly proposed spatial correlation model where a new set of location-dependent uncorrelated variables are defined over virtual grids to represent the original physical random variables via fitting. To compute the leakage current of a gate on the new set of variables, the new method uses the orthogonal polynomials based collocation method, which can be applied to any gate leakage models. The total leakage currents are then computed by simply summing up the resulting orthogonal polynomials (their coefficients) on the new set of variables for all gates. Experimental results show that the proposed method is about two orders of magnitude faster than the recently proposed grid-based method [3] with similar accuracy and many orders of magnitude times over the Monte Carlo method.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"11 1","pages":"481-486"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87125679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Pareto sampling: Choosing the right weights by derivative pursuit 帕累托抽样:通过导数追踪选择正确的权重
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837503
Amith Singhee, Pamela Castalino
{"title":"Pareto sampling: Choosing the right weights by derivative pursuit","authors":"Amith Singhee, Pamela Castalino","doi":"10.1145/1837274.1837503","DOIUrl":"https://doi.org/10.1145/1837274.1837503","url":null,"abstract":"The convex weighted-sum method for multi-objective optimization has the desirable property of not worsening the difficulty of the optimization problem, but can lead to very nonuniform sampling. This paper explains the relationship between the weights and the partial derivatives of the tradeoff surface, and shows how to use it to choose the right weights and uniformly sample largely convex tradeoff surfaces. It proposes a novel method, Derivative Pursuit (DP), that iteratively refines a simplicial approximation of the tradeoff surface by using partial derivative information to guide the weights generation. We demonstrate the improvements offered by DP on both synthetic and circuit test cases, including a 22 nm SRAM bitcell design problem with strict read and write yield constraints, and power and performance objectives.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"149 1","pages":"913-916"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85580336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A novel optimal single constant multiplication algorithm 一种新的最优单常数乘法算法
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837424
J. Thong, N. Nicolici
{"title":"A novel optimal single constant multiplication algorithm","authors":"J. Thong, N. Nicolici","doi":"10.1145/1837274.1837424","DOIUrl":"https://doi.org/10.1145/1837274.1837424","url":null,"abstract":"Existing optimal single constant multiplication (SCM) algorithms are limited to 19 bit constants. We propose an exact SCM algorithm. For 32 bit constants, the average run time is under 10 seconds. Optimality is ensured via an exhaustive search. The novelty of our algorithm is in how aggressive pruning is achieved by combining two SCM frameworks.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"32 1","pages":"613-616"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90081385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Cyber-physical energy systems: Focus on smart buildings 网络物理能源系统:关注智能建筑
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837464
J. Kleissl, Yuvraj Agarwal
{"title":"Cyber-physical energy systems: Focus on smart buildings","authors":"J. Kleissl, Yuvraj Agarwal","doi":"10.1145/1837274.1837464","DOIUrl":"https://doi.org/10.1145/1837274.1837464","url":null,"abstract":"Operating at the intersection of multiple sensing and control systems designed for occupant comfort, performability and operational efficiency, modern buildings represent a prototypical cyber-physical system with deeply coupled embedded sensing and networked information processing that has increasingly become part of our daily lives. In this paper, we look at modern buildings entirely as a cyber-physical energy system and examine the opportunities presented by the joint optimization of energy use by its occupants and information processing equipment. This paper makes two contributions: one, a careful examination of different types of buildings and their energy use; two, opportunities available to improve energy efficient operation through various strategies from lighting to computing. Using a modern 150,000 sq feet office building as a closed system, we detail different strategies to reduce energy use from LEED certification to zero net energy use.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"42 1","pages":"749-754"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86240932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 132
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