发布求助
文献互助 智能选刊 最新文献

Proceedings. Design Automation Conference最新文献

筛选
英文 中文
A parallel integer programming approach to global routing 全局路由的并行整数规划方法
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837323
Tai-Hsuan Wu, A. Davoodi, Jeff T. Linderoth
{"title":"A parallel integer programming approach to global routing","authors":"Tai-Hsuan Wu, A. Davoodi, Jeff T. Linderoth","doi":"10.1145/1837274.1837323","DOIUrl":"https://doi.org/10.1145/1837274.1837323","url":null,"abstract":"We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses at it core an existing integer programming (IP) formulation-both for routing each subproblem and for connecting them. Concurrent processing of the routing subproblems is desirable for effective parallelization. However, achieving no (or low) overflow global routing solutions without strong, coordinated algorithmic control is difficult. Our algorithm addresses this challenge via a patching phase that uses IP to connect partial routing solutions. Patching provides feedback to each routing subproblem in order to avoid overflow, later when attempting to connect them. The end result is a flexible and highly scalable distributed algorithm for global routing. The method is able to accept as input target runtimes for its various phases and produce high-quality solution within these limits. Computational results show that for a target runtime of 75 minutes, running on a computational grid of few hundred CPUs with 2GB memory, the algorithm generates higher quality solutions than competing methods in the open literature.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"23 1","pages":"194-199"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86809143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
An efficient dual algorithm for vectorless power grid verification under linear current constraints 线性电流约束下无矢量电网验证的有效对偶算法
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837484
Xuanxing Xiong, Jia Wang
{"title":"An efficient dual algorithm for vectorless power grid verification under linear current constraints","authors":"Xuanxing Xiong, Jia Wang","doi":"10.1145/1837274.1837484","DOIUrl":"https://doi.org/10.1145/1837274.1837484","url":null,"abstract":"Vectorless power grid verification makes it possible to evaluate worst-case voltage drops without enumerating possible current waveforms. Under linear current constraints, the vectorless power grid verification problem can be formulated and solved as a linear programming (LP) problem. However, previous approaches suffer from long runtime due to the large problem size. In this paper, we design the DualVD algorithm that efficiently computes the worst-case voltage drops in an RC power grid. Our algorithm combines a novel dual approach to solve the LP problem, and a preconditioned conjugate gradient power grid analyzer. Our dual approach exploits the structure of the problem to simplify its dual problem into a convex problem, which is then solved by the cutting-plane method. Experimental results show that our algorithm is extremely efficient - it takes less than an hour to complete the verification of a power grid with more than 50 K nodes and it takes less than 1 second to verify one node in a power grid with more than 500 K nodes.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"34 1","pages":"837-842"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86209160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Post-silicon validation opportunities, challenges and recent advances 后硅验证的机遇、挑战和最新进展
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837280
S. Mitra, S. Seshia, N. Nicolici
{"title":"Post-silicon validation opportunities, challenges and recent advances","authors":"S. Mitra, S. Seshia, N. Nicolici","doi":"10.1145/1837274.1837280","DOIUrl":"https://doi.org/10.1145/1837274.1837280","url":null,"abstract":"Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all bugs before manufacture. Post-silicon validation is a major challenge for future systems. Today, it is largely viewed as an art with very few systematic solutions. As a result, post-silicon validation is an emerging research topic with several exciting opportunities for major innovations in electronic design automation. In this paper, we provide an overview of the post-silicon validation problem and how it differs from traditional pre-silicon verification and manufacturing testing. We also discuss major postsilicon validation challenges and recent advances.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"25 1","pages":"12-17"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81375299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 156
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system 从集成电路的配电系统中导出的物理不可克隆功能的质量度量评价
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837336
Ryan L. Helinski, D. Acharyya, J. Plusquellic
{"title":"Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system","authors":"Ryan L. Helinski, D. Acharyya, J. Plusquellic","doi":"10.1145/1837274.1837336","DOIUrl":"https://doi.org/10.1145/1837274.1837336","url":null,"abstract":"The level of security provided by digital rights management functions and cryptographic protocols depend heavily on the security of an embedded secret key. The current practice of embedding the key as digital data in the integrated circuit (IC) weakens these security protocols because the keys can be learned through attacks. Physical unclonable functions (PUFs) are a recent alternative to storing digital keys on the IC. A PUF leverages the inherent manufacturing variations of an IC to define a random function. Given environmental variations such as temperature and supply noise, PUF quality criteria such as reproducibility and the level of randomness in the responses may be difficult to achieve for a given PUF circuit architecture. In this paper, we evaluate a PUF derived from the power distribution system of an IC with regard to a set of quality metrics including single-bit and collision probability and entropy. The analysis is carried out using data obtained from 36 chips fabricated in IBM's 65 nm SOI technology.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"36 1","pages":"240-243"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90207692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Find your flow: Increasing flow experience by designing “human” embedded systems 找到你的心流:通过设计“人性化”嵌入式系统来增加心流体验
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837428
Chen-Ling Chou, Anca M. Miron, R. Marculescu
{"title":"Find your flow: Increasing flow experience by designing “human” embedded systems","authors":"Chen-Ling Chou, Anca M. Miron, R. Marculescu","doi":"10.1145/1837274.1837428","DOIUrl":"https://doi.org/10.1145/1837274.1837428","url":null,"abstract":"In this paper, we argue that future systems need to be designed using a flexible user-centric design methodology geared primarily toward maximizing the user satisfaction (i.e., flow experience) rather than seeking mainly optimization of performance and power consumption. Compared to the traditional design, we aim at re-focusing the current design paradigm by placing the user behavior at the center of the design process and by using psychological variables such as user ability and motivation as the main drivers of this process. This allows systems to become more capable of promptly adapting to different users' needs and of enhancing short- and long-term user satisfaction. Preliminary results show the potential of this methodology for maximizing the users' positive experience when running embedded applications on multiprocessor platforms.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"101 2 1","pages":"619-620"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77754345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The evolution of SOC interconnect and How NOC Fits Within It SOC互连的演变以及NOC如何适应其中
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837354
B. Mathewson
{"title":"The evolution of SOC interconnect and How NOC Fits Within It","authors":"B. Mathewson","doi":"10.1145/1837274.1837354","DOIUrl":"https://doi.org/10.1145/1837274.1837354","url":null,"abstract":"In this paper, we describe “The Evolution of SOC Interconnect and How NOC Fits Within It” which is being presented during the “A Decade of NOC Research-Where Do We Stand?” session at DAC 2010. The presentation looks at the features that have helped shape the development of on-chip interconnect solutions. The evolution of NoC is considered alongside the evolution of the AMBA on-chip communication architecture, and consideration is given to the techniques that are considered most important.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"29 1","pages":"312-313"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81887312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation 片上电压调节输电网的权衡分析与优化
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837483
Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li
{"title":"Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation","authors":"Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li","doi":"10.1145/1837274.1837483","DOIUrl":"https://doi.org/10.1145/1837274.1837483","url":null,"abstract":"Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlevel power management. The quantitative understanding of such complex power delivery networks (PDNs) is hampered by the large network complexity and interactions between passive on-die/package-level circuits and a multitude of nonlinear active regulators. We develop a fast combined GPU-CPU analysis engine encompassing several simulation strategies, optimized for various subcomponents of the network. Using accurate quantitative analysis, we demonstrate the significant performance improvement brought by on-chip low-dropout regulators (LDOs) in terms of suppressing high-frequency local voltage droops and avoiding the mid-frequency resonance caused by off-chip inductive par-asitics. We perform comprehensive analysis on the tradeoffs among overhead of on-chip LDOs, maximum voltage droop and overall power efficiency. We conduct systematic design optimization by developing a simulation-based nonlinear optimization strategy that determines the optimal number of on-chip LDOs required and on-board input voltage, and the corresponding voltage droop and power efficiency for PDNs with multiple power domains.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"23 5 1","pages":"831-836"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78659004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
LUT-based FPGA technology mapping for reliability 基于lut的FPGA技术的可靠性映射
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837401
J. Cong, Kirill Minkovich
{"title":"LUT-based FPGA technology mapping for reliability","authors":"J. Cong, Kirill Minkovich","doi":"10.1145/1837274.1837401","DOIUrl":"https://doi.org/10.1145/1837274.1837401","url":null,"abstract":"As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very important at 45nm and beyond. One common defect point is in the lookup table (LUT) configuration bits, which are crucial to the correct operation of FPGAs. In this work we will present an error analysis technique that is able to efficiently calculate the number of critical bits needed to implement each LUT. We will perform this analysis using a scalable overlapping window-based method called DCOW (Don't-care Computation with Overlapping Windows), which allows for accurate and efficient don't-care lower bound calculations. This new windowing technique can approximate the complete don't cares within 2.34%, and can be used for many logic synthesis operations. In particular, we apply DCOW to our FPGA mapping algorithm to reduce the number of possible faults. This will allow the design to have a much higher success of functioning correctly when implemented on a faulty FPGA. By using our algorithm, we are able to reduce the number of possible faults by more than 12% with no area increase.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"12 1","pages":"517-522"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76686811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations 由于制造变化导致的失效速度路径段的后硅诊断
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837344
Lin Xie, A. Davoodi, K. Saluja
{"title":"Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations","authors":"Lin Xie, A. Davoodi, K. Saluja","doi":"10.1145/1837274.1837344","DOIUrl":"https://doi.org/10.1145/1837274.1837344","url":null,"abstract":"We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is applied after isolating the failing speedpaths which also incorporates post-silicon path-delay measurements for more accurate analysis. Our goal is to identify segments of the failing speedpaths that have a post-silicon delay larger than their estimated delays at the pre-silicon stage. We refer to such segments as “failing segments” and we rank them according to their degree of failure. Diagnosis of failing segments alleviates the problem of lack of observability inside a path. Moreover, root-cause analysis, and post-silicon tuning or repair, can be done more effectively by focusing on the failing segments. We propose an Integer Linear Programming formulation to breakdown a path into a set of non-failing segments, leaving the remaining to be likely-failing ones. Our algorithm yields a very high “diagnosis resolution” in identifying failing segments, and in ranking them.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"388 1","pages":"274-279"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76808963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Network on chip design and optimization using specialized influence models 利用专门的影响模型设计和优化芯片上的网络
Proceedings. Design Automation Conference Pub Date : 2010-06-13 DOI: 10.1145/1837274.1837431
Cristinel Ababei
{"title":"Network on chip design and optimization using specialized influence models","authors":"Cristinel Ababei","doi":"10.1145/1837274.1837431","DOIUrl":"https://doi.org/10.1145/1837274.1837431","url":null,"abstract":"In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-on-Chip (NoC). Our goal is to construct a versatile modeling framework that will help in the development and analysis of distributed and adaptive features for NoCs. As an application testbench, we use this framework to construct a design methodology for dynamic voltage and frequency scaling (DVFS). We also point out similarities of the proposed model with backpressure mechanisms that could be potentially exploited toward enhanced models for estimation and optimization of NoCs.","PeriodicalId":87346,"journal":{"name":"Proceedings. Design Automation Conference","volume":"111 1","pages":"625-626"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73985480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信