电路与系统学报最新文献_第10页

The synthesis of linear-phase multirate frequency-response-masking filters 线性相位多速率频率响应掩蔽滤波器的合成

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.612792

Y. Lim, Rui Yang

引用次数: 11

A novel very-high-output-impedance high-swing cascode stage and its applications 一种新型的超高输出阻抗高摆幅级联电路及其应用

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.621540

E. Tiiliharju, S. Zarabadi, M. Ismail, K. Halonen

引用次数: 4

A cell model of chaotic attractor 混沌吸引子的单元模型

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.621912

S. Qiu

引用次数: 4

A new motion estimation core dedicated to H.263 video coding H.263视频编码的一种新的运动估计核心

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.622018

G. Fujita, T. Onoye, I. Shirakawa

引用次数: 22

An error concealment scheme for MPEG-2 coded video sequences MPEG-2编码视频序列的错误隐藏方案

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.622079

S. Tsekeridou, I. Pitas, C. Le Buhan

引用次数: 11

Dynamic half rail differential logic for low power 动态半轨差动逻辑低功耗

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.621530

S. Choe, G. Rigby, G. Hellestrand

引用次数: 4

Quantum-dot cellular nonlinear networks: computing with locally-connected quantum dot arrays 量子点细胞非线性网络:局部连接量子点阵列的计算

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.608994

W. Porod, C. Lent, G. Tóth, H. Luo, Á. Csurgay, Y.-F. Huang, R.-W. Liu

引用次数: 15

On the dynamics and stable equilibria of anti-symmetric CNNs 反对称cnn的动态与稳定平衡

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.608820

B. Mirzai, D. Lím, G. Moschytz

引用次数: 1

Low-power digit-serial multipliers 低功耗数字串行乘法器

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.621599

Yun-Nan Chang, J. Satyanarayana, K. K. Parhi

{"title":"Low-power digit-serial multipliers","authors":"Yun-Nan Chang, J. Satyanarayana, K. K. Parhi","doi":"10.1109/ISCAS.1997.621599","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621599","url":null,"abstract":"Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (/spl les/4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"98 1","pages":"2164-2167 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81194043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A 1.2 V CMOS four-quadrant analog multiplier 一个1.2 V CMOS四象限模拟乘法器

电路与系统学报 Pub Date : 1997-06-09 DOI: 10.1109/ISCAS.1997.608684

Shuo-Yuan Hsiao, Chung-Yu Wu

引用次数: 11