Dynamic half rail differential logic for low power

Abstract

A new logic family which uses less power compared to conventional logic is described. Power reduction is achieved by recycling the charge from the evaluate cycle for the precharge cycle. The logic of each stage is pipelined anti the cascade chain operates on a four phase clock. Power metrics for both gate and overall power (sum of gate and clock power) are presented. Simulations demonstrate a reduction of 40% to 50% in the gate power consumption compared to conventional logic.