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Quasi-Atomic Layer Etching Technology for High Uniformity Etching Applications 准原子层蚀刻技术在高均匀性蚀刻中的应用
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282601
Y. Zhang, J. Chong, C. Wang, Q. Xie, D. Li
{"title":"Quasi-Atomic Layer Etching Technology for High Uniformity Etching Applications","authors":"Y. Zhang, J. Chong, C. Wang, Q. Xie, D. Li","doi":"10.1109/CSTIC49141.2020.9282601","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282601","url":null,"abstract":"This paper illustrated Quasi-Atomic Layer Etching (Q-ALE) process, based on Inductively Coupled Plasma (ICP) etching technology. Q-ALE process could solve several conventional plasma etching issues, for instance, Aspect Ratio Dependent Etching (ARDE) effect. Furthermore, Q-ALE process could achieve relatively high etching uniformity with low surface roughness and low etching damage for silicon and compound semiconductors etching applications.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"54 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91367817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of Influence of STI Profile on Harp Gap-Filling Performance STI型线对竖琴补隙性能的影响研究
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282412
Kai Wang, Zhigang Zhang, Ping Wang, Ling-zhi Xu, Shenzhou Lu, A. Tan, Zhenjie Qiao, K. Huang, Qimeng Wang, Duo Shan, Fan Zhang, Chang Fu, Zhaoyuan Zhao, Qin Sun
{"title":"Study of Influence of STI Profile on Harp Gap-Filling Performance","authors":"Kai Wang, Zhigang Zhang, Ping Wang, Ling-zhi Xu, Shenzhou Lu, A. Tan, Zhenjie Qiao, K. Huang, Qimeng Wang, Duo Shan, Fan Zhang, Chang Fu, Zhaoyuan Zhao, Qin Sun","doi":"10.1109/CSTIC49141.2020.9282412","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282412","url":null,"abstract":"HARP gap-filling performance is related with trench profile. In this paper, the influence of STI morphology on HARP gap-filling performance is studied. Both the slight undercut between top SiN and active area (AA), and top SiN CD, don't show impact on HARP gap-filling performance for the observed range. The side wall angle is key factor. For side wall angle of 89°, we have proved from both theory and experiment, that even 0.5° reduction of side wall angle can greatly reduce the STI void density.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"87 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77568748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monitoring Critical Process Steps in 3D NAND using Picosecond Ultrasonic Metrology with both Thickness and Sound Velocity Capabilities 使用具有厚度和声速能力的皮秒超声测量技术监测3D NAND中的关键工艺步骤
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282409
J. Dai, P. Mukundhan, R. Mair, M. Mehendale, Calvin Wang, E. Wang, C. Kim
{"title":"Monitoring Critical Process Steps in 3D NAND using Picosecond Ultrasonic Metrology with both Thickness and Sound Velocity Capabilities","authors":"J. Dai, P. Mukundhan, R. Mair, M. Mehendale, Calvin Wang, E. Wang, C. Kim","doi":"10.1109/CSTIC49141.2020.9282409","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282409","url":null,"abstract":"Amorphous carbon (a-C) based hard masks provide superior etch selectivity, chemical inertness, are mechanically strong, and have been used for etching deep, high aspect ratio features that conventional photoresists cannot withstand. Picosecond Ultrasonic Technology (PULSE™ Technology) has been widely used in thin metal film metrology because of its unique advantages, such as being a rapid, non-contact, non-destructive technology and its capabilities for simultaneous multiple layer measurement [1]. Simultaneous measurement of velocity and thickness for transparent and semi-transparent films offers a lot of potential for not only monitoring the process but offers insight into the device performance. In this paper, we show successful applications of Picosecond Ultrasonics in 3D NAND. This includes measurement of various thin metal films and simultaneous measurement of sound velocity and thickness for amorphous carbon films which has been widely used as hard mask materials.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"554 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77597924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IDT Structure Optimization Design based on ALN/SI Substrate for Saw Devices 基于ALN/SI衬底的Saw器件IDT结构优化设计
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282591
Kaixuan Li, F. Wang, Shuo Yan, Meng Deng, Huanhuan Di, Wei Li, Kailiang Zhang
{"title":"IDT Structure Optimization Design based on ALN/SI Substrate for Saw Devices","authors":"Kaixuan Li, F. Wang, Shuo Yan, Meng Deng, Huanhuan Di, Wei Li, Kailiang Zhang","doi":"10.1109/CSTIC49141.2020.9282591","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282591","url":null,"abstract":"In this work, aluminum nitride (A1N) film with good piezoelectric properties was grown on the silicon (Si) substrate as piezoelectric layer, and the properties of surface acoustic wave (SAW) devices with different interdigital transducer (IDT) structures were researched by using Rectangle function, Hanning function and Kaiser function. MATLAB and e-LINE plus software were used to generate layout files quickly and accurately. Devices with 300nm finger width were tested at room temperature and the results indicated that devices with Kaiser function structure show better resonant waveforms, the center frequency was up to 4.94GHz, the inhibition degree of sidelobe increased obviously to 43.53dB, and insertion loss was -5.87dB. This work play an active role in the design and research of high performance surface acoustic wave devices.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78139143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of Graph Convolution Network Based on Analog Rram 基于模拟存储器的图卷积网络的实现
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282441
Daqin Chen, Zongwei Wang, Shengyu Bao, Yimao Cai, Ru Huang
{"title":"Implementation of Graph Convolution Network Based on Analog Rram","authors":"Daqin Chen, Zongwei Wang, Shengyu Bao, Yimao Cai, Ru Huang","doi":"10.1109/CSTIC49141.2020.9282441","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282441","url":null,"abstract":"In this work, the implementation of Graph Convolutional Network (GCN) based on resistive switching memory is demonstrated through simulation. After training, the RRAM-based GCN can process a semi-supervised graph classification task. Further, the impacts of read noises and circuit bit-precision on the performance of GCN are analyzed. Results show the proposed GCN can reach high accuracy when bit-precisions; 4-bit. Moreover, read noise can severely affect accuracy.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"46 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76668961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Timing Violation as Dominant Reason for Failure of Clocked Digital Circuit Due to RF Interference in Supply 电源射频干扰导致数字时钟电路失效的主要原因是时序冲突
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282440
Shanshan Nong, Tao Su
{"title":"Timing Violation as Dominant Reason for Failure of Clocked Digital Circuit Due to RF Interference in Supply","authors":"Shanshan Nong, Tao Su","doi":"10.1109/CSTIC49141.2020.9282440","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282440","url":null,"abstract":"This paper covers our observations of the failure behavior of a clocked digital circuit with sinusoidal interference acting on its supply. Conventionally, it has been thought that interference causes mainly logic-level errors in digital circuits, with the average value of the interference determining the circuit delay. As the interference cycle time is much shorter than both the data path delay and clock cycle time, the average value of the interference is almost zero. However, it still causes a timing violation, rather than a logic-level error, in the circuit. This observation was at odds with conventional thinking. This behavior was confirmed with both transistor-level simulations and board-based measurements. The findings of the present study are important for determining the frequency response of the maximum tolerable interference amplitude of a digital circuit in the design phase","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"27 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74126116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Lead the Future : Semiconductor Evolution as Seen by CMP Manufacturers 引领未来:CMP制造商眼中的半导体演变
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282449
M. Tsujimura
{"title":"Lead the Future : Semiconductor Evolution as Seen by CMP Manufacturers","authors":"M. Tsujimura","doi":"10.1109/CSTIC49141.2020.9282449","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282449","url":null,"abstract":"The global situation has become increasingly uncertain and it has been a long time since the so-called VUCA era began. The semiconductor market, however, is now booming and semiconductor technology seems to have overcome its stagnation. The market has now entered the so-called Multi-driver era, driven by the IoT, Cloud, AI, Car, and 5G applications, collectively referred to as ICAC5, in addition to the former single set applications, such as PCs and mobile phones. Technologies adapted to the ICAC5 market have also been developed, and device development has been active in three directions: MM (More Moore), MtM (More than Moore), and BC (Beyond CMOS). With the development of semiconductor devices, new technologies are also required for manufacturing equipment such as CMP. Based on the uncertain global outlook, this paper provides an overview of device technology up to 2030 by showing the uniqueness of the semiconductor market, and presents as an example how the CMP process should evolve. Semiconductors are immortal as long as there is human desire. Semiconductors will continue to lead the future of technologies. And semiconductor manufacturing equipment will continue to support the evolution of semiconductor devices.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"52 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75772842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Speed Wafer Geometry on Silicon Wafers Using Wave Front Phase Imaging for Inline Metrology 利用波前相位成像技术在线测量硅片上的高速晶圆几何
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282496
J. Trujillo-Sevilla, J. Ramos-Rodríguez, J. Gaudestad
{"title":"High Speed Wafer Geometry on Silicon Wafers Using Wave Front Phase Imaging for Inline Metrology","authors":"J. Trujillo-Sevilla, J. Ramos-Rodríguez, J. Gaudestad","doi":"10.1109/CSTIC49141.2020.9282496","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282496","url":null,"abstract":"In this paper we introduce a new metrology technique for measuring wafer geometry on silicon wafers. Wafer geometry will be critical for the next generation integrated circuits (IC) for improvements in lithography overlay and to measure Nanotopography (NT) and roughness in conjunction with Chemical Mechanical Polishing (CMP). Wave Front Phase Imaging (WFPI) has high lateral resolution and is sensitive enough to measure NT and roughness on a silicon wafer by simply acquiring a single image snapshot of the entire wafer. WFPI is achieved by measuring the reflected light intensity from monochromatic uncoherent light at two different planes along the optical path with the same field of view. We show that the lateral resolution in the current system is 24µm though it can be pushed to less than 5µm by simply adding more pixels to the image sensor. Also, we show that the amplitude resolution limit is 0.3nm. First, 3 mirrors simulating a 50mm blank wafer with a known geometry was used to compare WFPI to the industry standard chromatic confocal microscopy. Then, a 2-inch wafer was measured while laying it on a flat sample holder without chucking it and NT and roughness was revealed by applying a double Gaussian high pass filter to the global topography data. The exposure time was 0.1 seconds and the time to analyze the data was just under 2 seconds while processing 4.34 million topography data points.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"33 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74904709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Gate Architecture Design in STI Based LDMOS 基于STI的LDMOS新型栅极结构设计
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282385
Ziquan Fang, Zhaozhao Xu, W. Qian
{"title":"A Novel Gate Architecture Design in STI Based LDMOS","authors":"Ziquan Fang, Zhaozhao Xu, W. Qian","doi":"10.1109/CSTIC49141.2020.9282385","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282385","url":null,"abstract":"Conventional STI based LDMOS devices always have an extended gate which performs as a poly plate on top of the STI. In this paper, we have proposed a novel LDMOS gate architecture with no overlap between gate and STI. Instead, the contacts landing on the STI perform as plate to obtain high off-state breakdown voltage (offBV). The novel LDMOS is compatible with CMOS process, and the offBV can be above 20V without additional drift implant mask. TCAD simulation is used to explain the underlying physics of the proposed novel architecture.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"51 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76335882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermal Modeling of Monolithic 3D ICs 单片三维集成电路的热建模
2020 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2020-06-26 DOI: 10.1109/CSTIC49141.2020.9282549
Baoli Peng, V. Pavlidis, Yuanqing Cheng
{"title":"Thermal Modeling of Monolithic 3D ICs","authors":"Baoli Peng, V. Pavlidis, Yuanqing Cheng","doi":"10.1109/CSTIC49141.2020.9282549","DOIUrl":"https://doi.org/10.1109/CSTIC49141.2020.9282549","url":null,"abstract":"Monolithic 3D integration can approach ultra-high device density compared to TSV -based integration owing to the sequential process. So it can effectively sustain Moore's law without resorting to costly technology shrinking. Nevertheless, heat dissipation problem in M3D ICs poses a big challenge, and is different from TSV -based counterparts due to close thermal coupling between neighboring tiers, which requires further investigations. In this work, we compare the thermal characteristics of M3D ICs to those of 2D ICs in 45nm technology node with a thermal model based on the finite element method. Experimental results show that the average and maximum temperature of M3D ICs is higher. We expect this work can invoke more research interests in thermal modeling and thermal aware physical design of M3D ICs.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"22 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81441655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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