2020 Pan Pacific Microelectronics Symposium (Pan Pacific)最新文献

{"title":"A Study on the Dynamic Bending Reliability of Chip-in-Fabrics(CIF) Packages Using Anisotropic Conductive Films (Acfs) Materials For Flexible Electronic Applications","authors":"Seung-Yoon Jung, K. Paik","doi":"10.23919/PanPacific48324.2020.9059461","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059461","url":null,"abstract":"In this study, flexible Chip-In-Fabric (CIF) assemblies using anisotropic conductive films (ACFs) and cover layer structure were demonstrated. Fabric substrates were fabricated by Cu pattern lamination method with additional Electroless Nickel Immersion Gold (ENIG) metal finish before laminating onto the fabrics. Thermo-compression (T/C) bonding method was used to bond the $50 mumathrm{m}$-thick Si chip on the fabric substrates using ACFs. After T/C bonding, stable ACFs joint interconnection was formed between chips and substrates. After polymer cover layer structure was applied, the minimum bending radius before chip crack drastically decreased down to 10 mm radius. In addition, a dynamic bending test was performed to evaluate the dynamic bending reliability of the CIF assemblies, and cross-section SEM analysis and digital image correlation (DIC) method were used to analyze the bending test results.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"238 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74486893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advances in Power Electronics","authors":"C. Bailey","doi":"10.23919/PanPacific48324.2020.9059348","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059348","url":null,"abstract":"Power electronics is seeing significant growth due to electrification of transport, and carbon reduction using renewable energy. Innovations in devices (e.g. wide bandgap materials such as Silicon Carbide and Gallium Nitride) provide the opportunity to design smaller power electronic systems that are highly efficient. A key to realizing these benefits is innovations in packaging and design tools. Traditional materials and packaging architectures need to address the new environments that they will be subjected to higher temperatures, frequencies, and inductances, etc. New design and modelling approaches will be required to support innovations in packaging and reliability predictions. This paper details some of the recent advances in power electronics systems and details some of the challenges that need to be overcome.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"39 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78963057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"In-Line Testing of Highly Panelized PCBAS with Parallel Functional Test","authors":"John VanNewkirk","doi":"10.23919/PanPacific48324.2020.9059454","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059454","url":null,"abstract":"As semiconductor manufactures continue deliver more capabilities in ever smaller packages, most circuit board assemblies are shrinking. High volume electronic modules are increasingly manufactured in panels of 10, 20, or even 40 identical boards. The increase in panel density is driving substantial efficiency and throughput gains on the SMT lines; however, the typical testing processes is unable to match this increased throughput. Traditional test process throughput can easily be 5–10x slower than production throughput for these boards. This mismatch in throughput capability is forcing manufacturers to choose between high levels of untested work in process (WIP) inventory or giving up the throughput gains by slowing down the SMT line. New technology is available to provide simultaneous electrical functional testing of all the boards in the panel, allowing test to occur in line with production. System architecture, application development, and integration will be discussed. Process benefits, including case studies, will be provided, as will industry trends that drive manufacturers to reduce human handling and scrap reworked boards. Lastly, the status of these technologies, current capabilities, limitations, and commercial rollout plans detailed.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"44 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80101051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Copper Electrodeposition by Hydrogen Evolution Assisted Electroplating (HEA) for Wearable Electronics","authors":"Sabrina M. Rosa-Ortiz, A. Takshi","doi":"10.23919/PanPacific48324.2020.9059338","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059338","url":null,"abstract":"A novel technique called hydrogen evolution assisted (HEA) electroplating, has dramatically shown enhancement to the deposition rate of copper compared to galvanostatic conventional electroplating methods, opening new venues for the direct integration of devices to fabrics leading to the development of useful wearable electronics. HEA can be used for both printing copper tracks on a multi-wall carbon nanotubes (MWCNTs) coated template tracks and soldering surface mount electronic devices (SMD) to such tracks, demonstrating its versatility to be used for specific applications in which fabric mutilation wants to be prevented. However, in this project we studied how copper deposition takes place at different voltage ranges using 1000 Denier Coated Cordura Nylon, Laminated Polyester Ripstop and 100% Virgin Vinyl in the constant presence of the hydrogen evolution technique. Cupric sulfate (CUSO4) and sulfuric acid (H2SO4) were used as the medium to allow a lateral deposition over a multi-wall carbon nanotube track of 0.1mm by the application of a voltage ranging between - 0.5V to −2.0V using a potentiostat to employ the cyclic voltammeter technique in order to achieve a uniform deposition. Structure of the fabrics and variation of the copper deposits with respect to the type of fabric used were observed using a scanning electron microscopy (SEM).","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"18 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85227990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"i4.0, are We Really Ready?","authors":"Keith Bryant","doi":"10.23919/panpacific48324.2020.9059503","DOIUrl":"https://doi.org/10.23919/panpacific48324.2020.9059503","url":null,"abstract":"The Internet of Things, as a concept, was officially named in 1999. One of the first examples of an Internet of Things was a Coca Cola machine, located at the Carnegie Melon University. Local programmers would connect by Internet to the refrigerated appliance and check to see if there was a drink available, and if it was cold, before making the trip. The term “Industrie 4.0” was used for the first time in 2011 at the Hannover Fair. In October 2012 the Working Group on Industry 4.0 presented a set of implementation recommendations to the German federal government. Industry 4.0” refers to the concept of factories in which machines are augmented with wireless connectivity and sensors, connected to a system that can visualise the entire production line and make decisions on its own. Industry 4.0 fosters what has been called a “smart factory”. Within modular structured smart factories, cyber-physical systems monitor physical processes, create a virtual copy of the physical world and make decentralized decisions. Over the Internet of Things, cyber-physical systems communicate and cooperate with each other and with humans in real-time both internally and across organizational services offered and used by participants of the value chain. So, it's been around for a while and is well defined with the keys being connectivity and ‘smart sensors’ to monitor and feedback data, we also see that this is NOT ‘lights out factory’ as it also mentions communicating and cooperating with humans, but not at what level. This paper will evaluate SMT production and inspection machines and attempt to define their status and potential to act as ‘smart sensors’, the first building blocks towards i4.0, this will lead to the answer to the question in the title.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"19 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89527250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabriciton of High Strength NiCo Alloy and Rh Coating Using Electroplating Method","authors":"Yong-soo Lee, Seo-Hyang Lee, Jae-Ho Lee","doi":"10.23919/PanPacific48324.2020.9059510","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059510","url":null,"abstract":"NiCo alloys are electroplated in sulfate bath. The concentration of cobalt sulfate and current density were varied to optimize the surface hardness. The properties of NiCo deposits were analyzed using field emission scanning electron microscopy (FESEM), energy dispersive spectroscopy (EDS) and X-ray diffraction (XRD). The surface hardness of the NiCo alloy was increased up to 500Hv at 24 w% Co in the deposits due to the grain refinement. The size of grain was reduced to 12 nm. The residual stress of the deposits was varied from tensile to compressive as the saccharine concentration increased. The zero residual stress was achieved at 0.05 g/L saccharine addition. The electrodeposition of rhodium (Rh) on silicon substrate at different current conditions were investigated. The cracks were found at high current density during the direct current (DC) plating. The pulse current (PC) plating were applied to avoid the formation of cracks on the deposits. Off time in the pulse plating relieved the residual stress of the Rh deposits and consequently the current conditions for the crack-free Rh deposits were obtained. Optimum pulse current (PC) condition is 5:5 (on:off) for the crack-free Rh electroplating.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"PP 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84773432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Feasibility of Plasmonic Circuits Merged with Silicon Integrated Circuits","authors":"M. Fukuda, Y. Tonooka, Y. Ishikawa","doi":"10.23919/PanPacific48324.2020.9059350","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059350","url":null,"abstract":"Plasmonic signal transmission via nanoscale plasmonic waveguides is a new technique with the potential to increase the information transfer capacity in silicon integrated circuits (ICs). During propagation, surface plasmon polaritons (SPPs) exhibit characteristics of a lightwave whose transmission loss is mainly determined by the collective oscillation of electrons. Using this lightwave aspect of SPPs, information can be transmitted using plasmonic signals and optical transmission circuits and networks can be built at the micro/nanoscale. This size scale correlates well with that of electronic circuits comprising metal-oxide-semiconductor field-effect transistors (MOSFETs). In this article, the feasibility of on-chip interconnects and other circuits were discussed and confirmed on the basis of previously developed plasmonic components. The first example examined herein was a wavelength-division-multiplexing circuit comprising a multiplexer and demultiplexer (in 1310 and 1550 nm-wavelength bands), discussed based on the experimental results for each component. Multiplexed signals at the multiplexer were guided into a single-mode waveguide, divided at the demultiplexer and then passed to the electronic circuits. The transmitted plasmonic signals were converted to electric signals at the slits etched on the gate electrode, thereby driving the MOSFET without photodetectors, whereupon the MOSFET-amplified signals were outputted to the electronic circuits. The second example was coherent signal transmission via plasmonic circuits. The signal transmission was performed using micro/nanoscale plasmonic circuits in a manner similar to those of optical fiber transmission systems. These coherent signal transmissions via plasmonic signals were experimentally confirmed, being detected and converted to electric signals at the slits etched on the gate electrode of the MOSFET and then outputted therefrom. These experimental examples confirmed the feasibility of plasmonic circuits integrated with MOSFETs. In plasmonic circuits, signal transmission loss is generally high compared to that of electric and lightwave signals. Herein, it was numerically confirmed again that the plasmonic signal transmission losses were lower than those of electric signals transmitted in electric circuits for plasmonic circuits not exceeding an area of a few hundred square micrometers. The loss of lightwave signals (e.g., transmitted in silicon waveguides) was much lower than those of plasmonic signals. However, as the waveguide width approached the cut-off wavelength, the loss quickly increased to be greater than that of plasmonic signals. This work indicates that plasmonic circuits have an advantage in nanoscale circuits. The circuits presented herein are currently too primitive for actual silicon IC applications, but are adequate to indicate the feasibility of merging plasmonic circuits with silicon ICs.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"59 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85730754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Origins of Silicon Valley: Why and How It Got Started","authors":"P. Wesling","doi":"10.23919/panpacific48324.2020.9059475","DOIUrl":"https://doi.org/10.23919/panpacific48324.2020.9059475","url":null,"abstract":"Silicon Valley - an area that encompasses San Francisco and its extended suburbs to the south, including San Jose - is commonly known as the tech capital of the world. When most people think of the Valley, they probably think of semiconductors, personal computers, software, biotech and self-driving cars. But it was a hub for innovation long before the rise of personal computing, or even the transistor. Some consider the start of Hewlett-Packard Company as the beginning of what would become Silicon Valley; others date the start of the story to the founding of William Shockley's silicon transistor company, Shockley Semiconductor Laboratory, in Mountain View. But the seeds for what was to become Silicon Valley were actually sown 50 years earlier.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"56 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81162439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Case Study of Nickel Dendritic Growth on Printed-Circuit Boards","authors":"Prabjit Singh, Madhana Sunder, Eric E Campbell, L. Palmer","doi":"10.23919/PanPacific48324.2020.9059398","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059398","url":null,"abstract":"Dendritic growth is a rare short-circuit electrochemical phenomenon that can occur on printed-circuit boards (PCBs) in the presence of ionic contamination, high humidity and voltage bias. The elevated temperatures at which most electronic hardware operate lowers the relative humidity enough to dry the surface contamination that under humid conditions approaching condensation would result in dendritic growth. Silver is most prone to dendritic growth followed by copper and tin. Nickel dendritic growth has rarely been reported. This paper is a case study of nickel dendritic growth under moisture condensation condition on freshly produced circuit boards contaminated with sulfuric acid etchant. The sulfuric acid contamination on the as-manufactured PCBs got trapped in the solder mask crevice and under high humidity condition spread out across the gap between gold-on-nickel edge connector contact pads. The paper describes the electrochemistry of nickel dendritic growth phenomenon in some detail and concludes that nickel dendrites will grow only when the relative humidity of the environment is near or higher than the deliquescent relative humidity of the contamination on the printed circuit board.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"42 4 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76510437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced Substrate Technology for Heterogeneous Integration","authors":"Yu-Hua Chen","doi":"10.23919/PanPacific48324.2020.9059363","DOIUrl":"https://doi.org/10.23919/PanPacific48324.2020.9059363","url":null,"abstract":"The rapid development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process, and even next generation of 5nm.[1] The I/O pitch of chip is reduced accordingly but the interconnection of build-up of IC carrier is still large to fit the IC interconnects (Fig. 1). In order to overcome the gap of I/O pitch between IC chip and carrier, the interposer technology has been considered as a solution to resolve the issue.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"53 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74043970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}