{"title":"采用并行功能测试的高板化PCBAS在线测试","authors":"John VanNewkirk","doi":"10.23919/PanPacific48324.2020.9059454","DOIUrl":null,"url":null,"abstract":"As semiconductor manufactures continue deliver more capabilities in ever smaller packages, most circuit board assemblies are shrinking. High volume electronic modules are increasingly manufactured in panels of 10, 20, or even 40 identical boards. The increase in panel density is driving substantial efficiency and throughput gains on the SMT lines; however, the typical testing processes is unable to match this increased throughput. Traditional test process throughput can easily be 5–10x slower than production throughput for these boards. This mismatch in throughput capability is forcing manufacturers to choose between high levels of untested work in process (WIP) inventory or giving up the throughput gains by slowing down the SMT line. New technology is available to provide simultaneous electrical functional testing of all the boards in the panel, allowing test to occur in line with production. System architecture, application development, and integration will be discussed. Process benefits, including case studies, will be provided, as will industry trends that drive manufacturers to reduce human handling and scrap reworked boards. Lastly, the status of these technologies, current capabilities, limitations, and commercial rollout plans detailed.","PeriodicalId":6691,"journal":{"name":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","volume":"44 1","pages":"1-10"},"PeriodicalIF":0.0000,"publicationDate":"2020-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"In-Line Testing of Highly Panelized PCBAS with Parallel Functional Test\",\"authors\":\"John VanNewkirk\",\"doi\":\"10.23919/PanPacific48324.2020.9059454\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As semiconductor manufactures continue deliver more capabilities in ever smaller packages, most circuit board assemblies are shrinking. High volume electronic modules are increasingly manufactured in panels of 10, 20, or even 40 identical boards. The increase in panel density is driving substantial efficiency and throughput gains on the SMT lines; however, the typical testing processes is unable to match this increased throughput. Traditional test process throughput can easily be 5–10x slower than production throughput for these boards. This mismatch in throughput capability is forcing manufacturers to choose between high levels of untested work in process (WIP) inventory or giving up the throughput gains by slowing down the SMT line. New technology is available to provide simultaneous electrical functional testing of all the boards in the panel, allowing test to occur in line with production. System architecture, application development, and integration will be discussed. Process benefits, including case studies, will be provided, as will industry trends that drive manufacturers to reduce human handling and scrap reworked boards. Lastly, the status of these technologies, current capabilities, limitations, and commercial rollout plans detailed.\",\"PeriodicalId\":6691,\"journal\":{\"name\":\"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)\",\"volume\":\"44 1\",\"pages\":\"1-10\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/PanPacific48324.2020.9059454\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 Pan Pacific Microelectronics Symposium (Pan Pacific)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/PanPacific48324.2020.9059454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In-Line Testing of Highly Panelized PCBAS with Parallel Functional Test
As semiconductor manufactures continue deliver more capabilities in ever smaller packages, most circuit board assemblies are shrinking. High volume electronic modules are increasingly manufactured in panels of 10, 20, or even 40 identical boards. The increase in panel density is driving substantial efficiency and throughput gains on the SMT lines; however, the typical testing processes is unable to match this increased throughput. Traditional test process throughput can easily be 5–10x slower than production throughput for these boards. This mismatch in throughput capability is forcing manufacturers to choose between high levels of untested work in process (WIP) inventory or giving up the throughput gains by slowing down the SMT line. New technology is available to provide simultaneous electrical functional testing of all the boards in the panel, allowing test to occur in line with production. System architecture, application development, and integration will be discussed. Process benefits, including case studies, will be provided, as will industry trends that drive manufacturers to reduce human handling and scrap reworked boards. Lastly, the status of these technologies, current capabilities, limitations, and commercial rollout plans detailed.