异构集成的先进衬底技术

Yu-Hua Chen
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引用次数: 0

摘要

半导体技术的快速发展和终端产品的多功能需求,推动IC代工行业向7nm节点制程,甚至下一代5nm方向发展。[1]芯片的I/O间距相应减小,但IC载波搭建的互连仍然很大,以适应IC互连(图1)。为了克服IC芯片与载波之间的I/O间距差距,interposer技术被认为是解决这一问题的一种方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Advanced Substrate Technology for Heterogeneous Integration
The rapid development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process, and even next generation of 5nm.[1] The I/O pitch of chip is reduced accordingly but the interconnection of build-up of IC carrier is still large to fit the IC interconnects (Fig. 1). In order to overcome the gap of I/O pitch between IC chip and carrier, the interposer technology has been considered as a solution to resolve the issue.
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