2018 IEEE International Solid - State Circuits Conference - (ISSCC)最新文献_第6页

A 14.5mm2 8nW −59.7dBm-sensitivity ultrasonic wake-up receiver for power-, area-, and interference-constrained applications 14.5mm2 8nW−59.7 dbm灵敏度超声唤醒接收器，适用于功率、面积和干扰受限的应用

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310380

Angad S. Rekhi, A. Arbabian

{"title":"A 14.5mm2 8nW −59.7dBm-sensitivity ultrasonic wake-up receiver for power-, area-, and interference-constrained applications","authors":"Angad S. Rekhi, A. Arbabian","doi":"10.1109/ISSCC.2018.8310380","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310380","url":null,"abstract":"The next generation of the Internet of Things is envisioned to include unobtrusive, distributed mm-sized nodes capable of sensing and communicating information about their surroundings. Wake-up receivers (WuRXs) — ultra-low-power receivers that monitor their environment for a wake-up signature — are an important part of this vision, as they can extend the lifetime of a wireless node by keeping it asleep until interrogated. The state of the art in WuRXs, measured in terms of sensitivity and power, has recently been advanced by streamlining the signal path to include fewer power-hungry gain stages and instead obtaining the gain at the chip-antenna interface [1,2]. This has led to excellent power-sensitivity performance, but the accompanying increase in size hampers the applicability of these techniques in size-conscious applications, such as surveillance, asset tracking, and ubiquitous sensing. Moreover, size-reduction methods based on RF antenna miniaturization are fundamentally limited by high antenna Qs at low size-to-wavelength ratios [3]; efficiently matching to these antennas requires, in turn, high-Q passives that are generally unavailable at mm-scale.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"44 1","pages":"454-456"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84586568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

SkyLake-SP: A 14nm 28-Core xeon® processor SkyLake-SP: 14纳米28核xeon®处理器

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310170

S. Tam, H. Muljono, Min Huang, Sitaraman V. Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, S. Vora, Eddie Wang

引用次数: 53

An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM 一种反f类CMOS压控振荡器，具有高q的一、二谐共振，1/f2- 1/f3相位噪声抑制，实现196.2dBc/Hz FOM

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310340

Chee-Cheow Lim, Jun Yin, Pui-in Mak, H. Ramiah, R. Martins

引用次数: 17

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs 用于集成rf数据转换器soc的16nm FinFET中具有54fsrms抖动的7.4至14ghz锁相环

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310342

D. Turker, Ade Bekele, P. Upadhyaya, B. Verbruggen, Ying Cao, Shaojun Ma, C. Erdmann, B. Farley, Y. Frans, Ken Chang

引用次数: 33

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor 在z14™企业处理器中使用关键路径传感器和片上分布式电源估计引擎来降低功耗

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310303

Christos Vezyrtzis, T. Strach, P. Chuang, P. Lobo, R. Rizzolo, Tobias Webel, Pawel Owczarczyk, A. Buyuktosunoglu, Ramon Bertran Monfort, D. Hui, Susan M. Eickhoff, M. Floyd, G. Salem, S. Carey, Stelios G. Tsapepas, P. Restle

引用次数: 13

A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS 采用40nm CMOS的帧脉宽调制的20Gb/s收发器

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310288

Sejun Jeon, Woohyun Kwon, Taehun Yoon, Jong-Hyeok Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae

{"title":"A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS","authors":"Sejun Jeon, Woohyun Kwon, Taehun Yoon, Jong-Hyeok Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae","doi":"10.1109/ISSCC.2018.8310288","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310288","url":null,"abstract":"Expanding signal bandwidths in high-speed links is increasing intersymbol interference (ISI), which necessitates the enhancement of spectral efficiency. Recently, various modulation schemes including pulse amplitude modulation (PAM) [1], pulsewidth modulation (PWM) [2], permutation modulation (PM) [3] and duo-binary signaling [4] have been investigated in high-speed wireline links to increase spectral efficiency. However, multi-level signaling schemes suffer from SNR reduction and tighter linearity requirements when compared to conventional NRZ signaling. In this work, a 20Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the SNR degradation without linearity requirement is presented. The FPWM scheme encodes data at the location and the width of pulses in a frame spanning multiple UIs while maintaining a minimum pulsewidth equal to 1UI. The test-chip achieves a coding gain of 33%, which allows the total throughput of 20Gb/s while keeping the baud rate of 15Gb/s. The equalization core incorporates programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver, to compensate for channel insertion loss of up to 12dB at the baud frequency. The transceiver IC is implemented in 40nm CMOS and consumes 90.6mW from a 0.9V supply.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"38 1","pages":"270-272"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82415516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

SC: Hardware approaches to machine learning and inference SC:机器学习和推理的硬件方法

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310415

D. Friedman

引用次数: 1

A phase-domain readout circuit for a CMOS-compatible thermal-conductivity-based carbon dioxide sensor 一种用于cmos兼容热导二氧化碳传感器的相域读出电路

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310319

Z. Cai, R. V. Veldhoven, H. Suy, G. D. Graaf, K. Makinwa, M. Pertijs

引用次数: 2

A recursive-memory brain-state classifier with 32-channel track-and-zoom Δ2 Σ ADCs and Charge-Balanced Programmable Waveform Neurostimulators 递归记忆脑状态分类器与32通道跟踪和缩放Δ2 Σ adc和电荷平衡可编程波形神经刺激器

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310301

Gerard O’Leary, Mohammad Reza Pazhouhandeh, Michael Chang, David M. Groppe, T. Valiante, N. Verma, R. Genov

引用次数: 30

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications 16Gb/s/引脚8Gb GDDR6 DRAM，带宽扩展技术，适用于高速应用

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310258

Kyu-Dong Hwang, Boram Kim, Sangyeon Byeon, Kyu-Young Kim, Daehan Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-young Jang, Seung-Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, J. Chun, Jonghoon Oh, Jinkook Kim, S. Lee

{"title":"A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications","authors":"Kyu-Dong Hwang, Boram Kim, Sangyeon Byeon, Kyu-Young Kim, Daehan Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-young Jang, Seung-Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, J. Chun, Jonghoon Oh, Jinkook Kim, S. Lee","doi":"10.1109/ISSCC.2018.8310258","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310258","url":null,"abstract":"Recently the demand for high-bandwidth graphic DRAM, for game consoles and graphic cards, has dramatically increased due to the development of virtual reality, artificial intelligence, deep learning, autonomous driving cars, etc. These applications require greater data transfer speeds than pervious devices, GDDR5 [1] and GDDR5X [2], which are limited to 12Gb/s/pin. This paper introduces an 8Gb GDDR6 operating at up to 16Gb/s/pin. To exceed the prior speed limit various bandwidth extension techniques are proposed. WCK is driven with a dividing scheme to overcome speed limitations and to reduce power consumption. In addition, a dual-band architecture with different types of nibble drivers is proposed in order to cover stability of CML-to-CMOS in all frequency regions; CML nibble is used for high-speed, while CMOS nibble is used for low-speed. A DC-split scheme is implemented for duty-cycle correction and skew compensation. The bandwidth of the high-frequency divider is extended by using a proposed mode-changed flip-flop. The receiver uses a loop-unrolled one-tap decision-feedback equalizer (DFE) designed to eliminate channel inter-symbol interference (ISI). A two-stage pre-amplifier is also used for bandwidth extension. The transmitter uses a 4:1 multiplexer using a half-rate sampler, where a 1UI pulse is unnecessary to minimize the full-rate operation. To secure on-chip signal transmission characteristic, the bandwidth limitation of transistor in a DRAM process is extended by adopting an on-chip feedback EQ filter.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"240 1","pages":"210-212"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86700642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14