A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs

Direct-RF data converters [1,2] have seen increased adoption in remote-radio-head TX and RX, due to their unparalleled bandwidth and flexibility. However, since these converters need to directly synthesize and sample multi-GHz radio signals, the sampling clock must exhibit excellent phase-noise performance, to minimize self- and adjacent-channel mixing, and strong suppression of reference and harmonic spurs, to meet stringent out-of-band emissions and minimize aliased energy. Furthermore, a wide range of sampling frequencies is required for the flexibility to cover multiple bands. Due to these stringent requirements, typically, external PLLs are employed, adding to the BOM cost. This work presents techniques for a fully integrated 7.4-to-14GHz PLL in 16nm FinFET that has 54fsrms jitter to satisfy the low noise requirements of RF data converters.