SkyLake-SP: 14纳米28核xeon®处理器

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI:10.1109/ISSCC.2018.8310170

S. Tam, H. Muljono, Min Huang, Sitaraman V. Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, S. Vora, Eddie Wang

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引用次数: 53

摘要

SkyLake-SP (Scalable Performance)，代号SKX，是采用Intel®14nm三栅极CMOS技术制造的下一代至强®服务器处理器，具有11金属层[1,2]。SKX处理器家族有三种内核计数配置。每个SKX核心都伴随着1MB的专用L2(第二级缓存)和1.375MB的非排他L3(第三级缓存)。SKX处理器的最大配置为28核，支持6个DDR4通道(2666MT/s)， 3×20-lanes UPI处理器到处理器链路(10.4GT/s)和x48+4 PCIE链路(8GT/s)。SKX支持芯片上集成电压调节器(FIVR)实现的每核功率性能优化[3,4]。一种新的二维同步模上MESH结构将所有模上组件互连起来。图2.1.1显示了SKX处理器的整体架构。

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SkyLake-SP: A 14nm 28-Core xeon® processor

SkyLake-SP (Scalable Performance), code name SKX, is the next generation Xeon® server processor fabricated on the Intel® 14nm tri-gate CMOS technology with 11-metal layers [1,2]. The SKX processor family has three core-count configurations. Each SKX core is accompanied by 1MB of dedicated L2 (2nd level cache) and 1.375MB of non-exclusive L3 (3rd level cache). At its maximum configuration of 28 cores, the SKX processor supports 6 DDR4 channels (2666MT/s), 3×20-lanes UPI processor-to-processor links (10.4GT/s) and x48+4 PCIE links (8GT/s). SKX supports per-core power-performance optimization enabled by on-die integrated voltage regulators (FIVR) [3, 4]. A new 2-dimensional synchronous on-die MESH fabric interconnects all the on-die components. Fig. 2.1.1 shows the overall architecture of the SKX processor.

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2018 IEEE International Solid - State Circuits Conference - (ISSCC)

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