A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS

Abstract

Expanding signal bandwidths in high-speed links is increasing intersymbol interference (ISI), which necessitates the enhancement of spectral efficiency. Recently, various modulation schemes including pulse amplitude modulation (PAM) [1], pulsewidth modulation (PWM) [2], permutation modulation (PM) [3] and duo-binary signaling [4] have been investigated in high-speed wireline links to increase spectral efficiency. However, multi-level signaling schemes suffer from SNR reduction and tighter linearity requirements when compared to conventional NRZ signaling. In this work, a 20Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the SNR degradation without linearity requirement is presented. The FPWM scheme encodes data at the location and the width of pulses in a frame spanning multiple UIs while maintaining a minimum pulsewidth equal to 1UI. The test-chip achieves a coding gain of 33%, which allows the total throughput of 20Gb/s while keeping the baud rate of 15Gb/s. The equalization core incorporates programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver, to compensate for channel insertion loss of up to 12dB at the baud frequency. The transceiver IC is implemented in 40nm CMOS and consumes 90.6mW from a 0.9V supply.