2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)最新文献_第4页

TZSlicer: Security-aware dynamic program slicing for hardware isolation TZSlicer:用于硬件隔离的安全感知动态程序切片

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383886

Mengmei Ye, Jonathan M. Sherman, W. Srisa-an, Sheng Wei

{"title":"TZSlicer: Security-aware dynamic program slicing for hardware isolation","authors":"Mengmei Ye, Jonathan M. Sherman, W. Srisa-an, Sheng Wei","doi":"10.1109/HST.2018.8383886","DOIUrl":"https://doi.org/10.1109/HST.2018.8383886","url":null,"abstract":"To address security issues related to information leakage, microprocessor designers and manufacturers such as ARM and Intel have introduced hardware isolation-based technologies to support secure software execution. However, utilizing such technologies often requires significant efforts to design new applications or refactor existing applications to adhere to the usage protocols. Developers also need to clearly distinguish code sections that can manipulate sensitive data and relocate them to the secure execution environment. These processes can be laborious and error-prone, since over-protection can result in poor application performance and high resource usage, and under-protection may cause exploitable security vulnerabilities. In this paper, we introduce TZSlicer, a framework to automatically identify code that must be protected based on a sensitive variable list provided by developers. TZSlicer automatically identifies code sections that can process sensitive data, extracts those sections from the original program, and creates harness in the original and extracted code sections so that they can interface with each other. We develop a prototype of TZSlicer to support slicing of C programs at function, code block, and code line levels. Also, we identify optimization opportunities to improve the context switching overhead of TZSlicer via applying loop unrolling and variable renaming. We evaluate TZSlicer using seven real-world programs, and the evaluation results indicate that TZSlicer is effective in protecting sensitive data without incurring significant runtime and resource usage overheads.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"28 1","pages":"17-24"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89371456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Direct read of idle block RAM from FPGAs utilizing photon emission microscopy 利用光子发射显微镜从fpga直接读取空闲块RAM

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383889

Jacob Couch, Nicole Whewell, A. Monica, S. Papadakis

{"title":"Direct read of idle block RAM from FPGAs utilizing photon emission microscopy","authors":"Jacob Couch, Nicole Whewell, A. Monica, S. Papadakis","doi":"10.1109/HST.2018.8383889","DOIUrl":"https://doi.org/10.1109/HST.2018.8383889","url":null,"abstract":"In many reverse engineering efforts, side channels have been utilized to extract both design information and data from integrated circuits. In this paper, a technique is demonstrated to recover data by directly reading idle SRAM cells within an FPGA, without engaging the read circuitry. This is accomplished using photon emission microscopy to capture the photons that are emitted as leakage currents flow from the source to the drain of NMOS transistors within the SRAM cell. Depending on whether a 0 or 1 state is stored in a particular cell, the location of the emitting transistor is different. The read circuity in many integrated circuits cannot be easily activated in a repeatable pattern, thus forming need to access the contents of idle SRAM cells. This was evaluated and refined on a 220 nm process node FPGA. We discuss the physics of photon emission in these devices and the consequences for successful imaging of SRAM contents. Through initial investigations and calculations, we predict that extraction of data from idle SRAM can be conducted on more modern parts. Through an extension of this technique, data such as encryption keys, state information, and restricted variables that would not be accessible through traditional bitstream and firmware reverse engineering efforts can be extracted from the integrated circuit. This information can then be utilized to ensure the integrity of a system, or as a threat to the integrity of the system.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"19 1","pages":"41-48"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90319060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Secure chip odometers using intentional controlled aging 安全芯片里程表使用故意控制老化

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383898

N. E. C. Akkaya, B. Erbagci, K. Mai

{"title":"Secure chip odometers using intentional controlled aging","authors":"N. E. C. Akkaya, B. Erbagci, K. Mai","doi":"10.1109/HST.2018.8383898","DOIUrl":"https://doi.org/10.1109/HST.2018.8383898","url":null,"abstract":"Electronics counterfeiting is a significant and growing problem for electronics manufacturers, system integrators, and end customers. The widespread prevalence of counterfeit electronics in the manufacturing supply chain raises significant security concerns in both the defense and civilian sectors. The threat ranges from relatively simple IC remarking, in order to sell parts at a higher price or to recycle parts from discarded equipment, to wholesale reverse-engineering/copying of designs and manufacturing of cloned ICs and systems. To combat IC counterfeiting, we propose secure chip odometers to provide ICs with both a secure gauge of use/age and an authentication of provenance to enable simple, secure, robust differentiation between genuine and counterfeit parts. The secure chip odometers have chained binary aging elements (BAE) to measure use and age of the chip. In our proposed design, BAEs that use hot carrier injection (HCI) to measure age/use are designed and taped-out in a 65 nm bulk CMOS process. For characterization purposes, the taped-out chips have an array of 500 modular BAEs and a self-aging system with 16 modular BAEs. The modularity of the design provides 693 possible combinations for different stress current and current density values. The test chip dimensions are 1.2mm by 1.7mm with 78 pads, and each modular BAE has an area of 52.5μm2. They can be stressed with currents ranging from 40μA to 1.3mA at the 2.5V nominal stress voltage.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"34 1","pages":"111-117"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81446097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

RF-PUF: IoT security enhancement through authentication of wireless nodes using in-situ machine learning RF-PUF:通过使用原位机器学习对无线节点进行认证来增强物联网安全性

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383916

Baibhab Chatterjee, D. Das, Shreyas Sen

{"title":"RF-PUF: IoT security enhancement through authentication of wireless nodes using in-situ machine learning","authors":"Baibhab Chatterjee, D. Das, Shreyas Sen","doi":"10.1109/HST.2018.8383916","DOIUrl":"https://doi.org/10.1109/HST.2018.8383916","url":null,"abstract":"Physical unclonable functions (PUF) in silicon exploit die-to-die manufacturing variations during fabrication for uniquely identifying each die. Since it is practically a hard problem to recreate exact silicon features across dies, a PUF-based authentication system is robust, secure and cost-effective, as long as bias removal and error correction are taken into account. In this work, we utilize the effects of inherent process variation on analog and radio-frequency (RF) properties of multiple wireless transmitters (Tx) in a sensor network, and detect the features at the receiver (Rx) using a deep neural network based framework. The proposed mechanism/ framework, called RF-PUF, harnesses already-existing RF communication hardware and does not require any additional PUF-generation circuitry in the Tx for practical implementation. Simulation results indicate that the RF-PUF framework can distinguish up to 10000 transmitters (with standard foundry defined variations for a 65 nm process, leading to non-idealities such as LO offset and I-Q imbalance) under varying channel conditions, with a probability of false detection < 10−3.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"66 1","pages":"205-208"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83248243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Value prediction for security (VPsec): Countering fault attacks in modern microprocessors 安全性的值预测(VPsec):对抗现代微处理器中的故障攻击

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383922

Rami Sheikh, Rosario Cammarota, Wenjia Ruan

引用次数: 2

Delay model and machine learning exploration of a hardware-embedded delay PUF 硬件嵌入式延迟PUF的延迟模型和机器学习探索

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383905

Wenjie Che, M. Martínez‐Ramón, F. Saqib, J. Plusquellic

引用次数: 13

An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms 一种有效的基于sat的短周期密码算法

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383892

E. Dubrova, M. Teslenko

引用次数: 3

B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection B-TREPID:带PUF和完整性检测的无电池防篡改信封

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383890

Vincent Immler, J. Obermaier, Martin König, Matthias Hiller, G. Sigl

{"title":"B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection","authors":"Vincent Immler, J. Obermaier, Martin König, Matthias Hiller, G. Sigl","doi":"10.1109/HST.2018.8383890","DOIUrl":"https://doi.org/10.1109/HST.2018.8383890","url":null,"abstract":"Protecting embedded devices against physical attacks is a challenging task since the attacker has control of the device in a hostile environment. To address this issue, current countermeasures typically use a battery-backed tamper-respondent envelope that encloses the entire device to create a trusted compartment. However, the battery affects the system's robustness and weight, and also leads to difficulties with the security mechanism while shipping the device. In contrast, we present a batteryless tamper-resistant envelope, which contains a fine mesh of electrodes, and its complementary security concept. An evaluation unit checks the integrity of the sensor mesh by detecting short and open circuits. Additionally, it measures the capacitances of the mesh. Once its preliminary integrity is confirmed, a cryptographic key is derived from the capacitive measurements that represent a PUF, to decrypt and authenticate the firmware of the enclosed host system. We demonstrate the feasibility of our concept, provide details on the layout and electrical properties of the batteryless envelope, and explain the underlying security architecture. Practical results from a set of manufactured envelopes facilitate future research.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"22 1","pages":"49-56"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87334424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Syndrome: Spectral analysis for anomaly detection on medical IoT and embedded devices 症候群:用于医疗物联网和嵌入式设备异常检测的光谱分析

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-04-01 DOI: 10.1109/HST.2018.8383884

Nader Sehatbakhsh, Monjur Alam, A. Nazari, A. Zajić, Milos Prvulović

{"title":"Syndrome: Spectral analysis for anomaly detection on medical IoT and embedded devices","authors":"Nader Sehatbakhsh, Monjur Alam, A. Nazari, A. Zajić, Milos Prvulović","doi":"10.1109/HST.2018.8383884","DOIUrl":"https://doi.org/10.1109/HST.2018.8383884","url":null,"abstract":"Recent advances in embedded and IoT (internet-of-things) technologies are rapidly transforming health-care solutions and we are headed to a future of smaller, smarter, wearable and connected medical devices. IoT and advanced health sensors provide more convenience to patients and physicians. Where physicians can now wirelessly and automatically monitor patient's state. While these medical embedded devices provide a lot of new opportunities to improve the health care system, they also introduce a new set of security risks since they are connected to networks. More importantly, these devices are extremely hardware- and power-constrained, which in turn makes securing these devices more complex. Implementing complex malware detectors or anti-virus on these devices is either very costly or infeasible due to these limitations on power and resources. In this paper, we propose a new framework called SYNDROME for “externally” monitoring medical embedded devices. Our malware detector uses electromagnetic (EM) signals involuntary generated by the device as it executes a (medical) application in the absence of malware, and analyzes them to build a reference model. It then monitors the EM signals generated by the device during execution and reports an error if there is a statistically significant deviation from the reference model. To evaluate Syndrome, we use open-source software to implement a real-world medical device, called a Syringe Pump, on a variety of well-known embedded/IoT devices including Arduino Uno, FPGA Nios II soft-core, and two Linux IoT mini-computers: OlimexA13 and TS-7250. We also implement a control-flow hijack attack on SyringePump and use Syndrome to detect and stop the attack. Our experimental results show that using Syndrome, we can detect the attack for all the four devices with excellent accuracy (i.e. 0% false positive and 100% true positive) within few milliseconds after the attack starts.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"25 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83372218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

SAT-based reverse engineering of gate-level schematics using fault injection and probing 基于sat的门级原理图逆向工程的故障注入和探测

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2018-02-24 DOI: 10.1109/HST.2018.8383918

S. Keshavarz, Falk Schellenberg, Bastian Richter, C. Paar, Daniel E. Holcomb

{"title":"SAT-based reverse engineering of gate-level schematics using fault injection and probing","authors":"S. Keshavarz, Falk Schellenberg, Bastian Richter, C. Paar, Daniel E. Holcomb","doi":"10.1109/HST.2018.8383918","DOIUrl":"https://doi.org/10.1109/HST.2018.8383918","url":null,"abstract":"Gate camouflaging is a known security enhancement technique that tries to thwart reverse engineering by hiding the functions of gates or the connections between them. A number of works on SAT-based attacks have shown that it is often possible to reverse engineer a circuit function by combining a camouflaged circuit model and the ability to have oracle access to the obfuscated combinational circuit. Especially in small circuits it is easy to reverse engineer the circuit function in this way, but SAT-based reverse engineering techniques provide no guarantees of recovering a circuit that is gate-by-gate equivalent to the original design. In this work we show that an attacker who doesn't know gate functions or connections of an aggressively camouflaged circuit cannot learn the correct gate-level schematic even if able to control inputs and probe all combinational nodes of the circuit. We then present a stronger attack that extends SAT-based reverse engineering with fault analysis to allow an attacker to recover the correct gate-level schematic. We analyze our reverse engineering approach on an S-Box circuit.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"27 1","pages":"215-220"},"PeriodicalIF":0.0,"publicationDate":"2018-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83171847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9