{"title":"安全芯片里程表使用故意控制老化","authors":"N. E. C. Akkaya, B. Erbagci, K. Mai","doi":"10.1109/HST.2018.8383898","DOIUrl":null,"url":null,"abstract":"Electronics counterfeiting is a significant and growing problem for electronics manufacturers, system integrators, and end customers. The widespread prevalence of counterfeit electronics in the manufacturing supply chain raises significant security concerns in both the defense and civilian sectors. The threat ranges from relatively simple IC remarking, in order to sell parts at a higher price or to recycle parts from discarded equipment, to wholesale reverse-engineering/copying of designs and manufacturing of cloned ICs and systems. To combat IC counterfeiting, we propose secure chip odometers to provide ICs with both a secure gauge of use/age and an authentication of provenance to enable simple, secure, robust differentiation between genuine and counterfeit parts. The secure chip odometers have chained binary aging elements (BAE) to measure use and age of the chip. In our proposed design, BAEs that use hot carrier injection (HCI) to measure age/use are designed and taped-out in a 65 nm bulk CMOS process. For characterization purposes, the taped-out chips have an array of 500 modular BAEs and a self-aging system with 16 modular BAEs. The modularity of the design provides 693 possible combinations for different stress current and current density values. The test chip dimensions are 1.2mm by 1.7mm with 78 pads, and each modular BAE has an area of 52.5μm2. They can be stressed with currents ranging from 40μA to 1.3mA at the 2.5V nominal stress voltage.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"34 1","pages":"111-117"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Secure chip odometers using intentional controlled aging\",\"authors\":\"N. E. C. Akkaya, B. Erbagci, K. Mai\",\"doi\":\"10.1109/HST.2018.8383898\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Electronics counterfeiting is a significant and growing problem for electronics manufacturers, system integrators, and end customers. The widespread prevalence of counterfeit electronics in the manufacturing supply chain raises significant security concerns in both the defense and civilian sectors. The threat ranges from relatively simple IC remarking, in order to sell parts at a higher price or to recycle parts from discarded equipment, to wholesale reverse-engineering/copying of designs and manufacturing of cloned ICs and systems. To combat IC counterfeiting, we propose secure chip odometers to provide ICs with both a secure gauge of use/age and an authentication of provenance to enable simple, secure, robust differentiation between genuine and counterfeit parts. The secure chip odometers have chained binary aging elements (BAE) to measure use and age of the chip. In our proposed design, BAEs that use hot carrier injection (HCI) to measure age/use are designed and taped-out in a 65 nm bulk CMOS process. For characterization purposes, the taped-out chips have an array of 500 modular BAEs and a self-aging system with 16 modular BAEs. The modularity of the design provides 693 possible combinations for different stress current and current density values. The test chip dimensions are 1.2mm by 1.7mm with 78 pads, and each modular BAE has an area of 52.5μm2. They can be stressed with currents ranging from 40μA to 1.3mA at the 2.5V nominal stress voltage.\",\"PeriodicalId\":6574,\"journal\":{\"name\":\"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)\",\"volume\":\"34 1\",\"pages\":\"111-117\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HST.2018.8383898\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HST.2018.8383898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Secure chip odometers using intentional controlled aging
Electronics counterfeiting is a significant and growing problem for electronics manufacturers, system integrators, and end customers. The widespread prevalence of counterfeit electronics in the manufacturing supply chain raises significant security concerns in both the defense and civilian sectors. The threat ranges from relatively simple IC remarking, in order to sell parts at a higher price or to recycle parts from discarded equipment, to wholesale reverse-engineering/copying of designs and manufacturing of cloned ICs and systems. To combat IC counterfeiting, we propose secure chip odometers to provide ICs with both a secure gauge of use/age and an authentication of provenance to enable simple, secure, robust differentiation between genuine and counterfeit parts. The secure chip odometers have chained binary aging elements (BAE) to measure use and age of the chip. In our proposed design, BAEs that use hot carrier injection (HCI) to measure age/use are designed and taped-out in a 65 nm bulk CMOS process. For characterization purposes, the taped-out chips have an array of 500 modular BAEs and a self-aging system with 16 modular BAEs. The modularity of the design provides 693 possible combinations for different stress current and current density values. The test chip dimensions are 1.2mm by 1.7mm with 78 pads, and each modular BAE has an area of 52.5μm2. They can be stressed with currents ranging from 40μA to 1.3mA at the 2.5V nominal stress voltage.