2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)最新文献_第6页

DWE: Decrypting Learning with Errors with Errors DWE:用错误解密学习

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3196032

S. Bian, Masayuki Hiromoto, Takashi Sato

引用次数: 4

Dynamic Management of Key States for Reinforcement Learning-assisted Garbage Collection to Reduce Long Tail Latency in SSD 基于强化学习辅助垃圾回收的关键状态动态管理以减少SSD长尾延迟

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3196034

Won-Kyung Kang, S. Yoo

引用次数: 20

CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator CMP-PIM:一种基于比较器的高效内存处理神经网络加速器

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3196009

Shaahin Angizi, Zhezhi He, A. S. Rakin, Deliang Fan

引用次数: 75

Extensive Evaluation of Programming Models and ISAs Impact on Multicore So Error Reliability 编程模型和isa对多核So错误可靠性影响的广泛评估

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3196050

F. Rosa, Vitor V. Bandeira, R. Reis, Luciano Ost

引用次数: 6

Efficient Batch Statistical Error Estimation for Iterative Multi-level Approximate Logic Synthesis 迭代多级近似逻辑综合的有效批量统计误差估计

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3196038

Sanbao Su, Yi Wu, Weikang Qian

引用次数: 21

A Neuromorphic Design Using Chaotic Mott Memristor with Relaxation Oscillation 基于松弛振荡的混沌Mott忆阻器的神经形态设计

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3195977

Bonan Yan, Xiong Cao, Hai Li

引用次数: 2

Architecture Decomposition in System Synthesis of Heterogeneous Many-Core Systems 异构多核系统综合中的体系结构分解

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3195995

Valentina Richthammer, T. Schwarzer, S. Wildermann, J. Teich, Michael Glass

{"title":"Architecture Decomposition in System Synthesis of Heterogeneous Many-Core Systems","authors":"Valentina Richthammer, T. Schwarzer, S. Wildermann, J. Teich, Michael Glass","doi":"10.1145/3195970.3195995","DOIUrl":"https://doi.org/10.1145/3195970.3195995","url":null,"abstract":"Determining feasible application mappings for Design Space Exploration (DSE) and run-time embedding is a challenge for modern many-core systems. The underlying NP-complete system-synthesis problem faces tremendously complex problem instances due to the hundreds of heterogeneous processing elements, their communication infrastructure, and the resulting number of mapping possibilities. Thus, we propose to employ a search-space splitting (SSS) technique using architecture decomposition to increase the performance of existing design-time and run-time synthesis approaches. The technique first restricts the search for application embeddings to selected sub-architectures at substantially reduced complexity; therefore, the complete architecture needs to be searched only in case no embedding is found on any sub-system. Furthermore, we introduce a basic learning mechanism to detect promising sub-architectures and subsequently restrict the search to those. We exemplify the SSS for a SAT-based and a problem-specific backtracking-based system synthesis as part of DSE for NoC-based many-core systems. Experimental results show drastically reduced execution times (≈ 15–50 × on a 24×24 architecture) and an enhanced quality of the embedding, since less mappings (≈ 20–40 ×, compared to the non-decomposing procedures) need to be discarded due to a timeout.","PeriodicalId":6491,"journal":{"name":"2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)","volume":"19 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79942829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Noise-Aware DVFS Transition Sequence Optimization for Battery-Powered IoT Devices 电池供电物联网设备的噪声感知DVFS转换序列优化

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3196080

Shaoheng Luo, Cheng Zhuo, H. Gan

{"title":"Noise-Aware DVFS Transition Sequence Optimization for Battery-Powered IoT Devices","authors":"Shaoheng Luo, Cheng Zhuo, H. Gan","doi":"10.1145/3195970.3196080","DOIUrl":"https://doi.org/10.1145/3195970.3196080","url":null,"abstract":"Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well known for their bursty workloads and limited energy storage — usually in the form of tiny batteries. To ensure battery lifetime, DVFS has become an essential technique in such SoC chips. With continuously decreasing supply level, noise margins in these devices are already being squeezed. During DVFS transition, large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles, and induces large Ldi/dt noise, thereby stressing the power delivery network (PDN). Due to the limited area and cost target, adding additional decap to mitigate such noise is usually challenging. A common approach is to gradually introduce/remove the additional clock cycles to increase or reduce the clock frequency in steps, a.k.a., clock skipping. However, such a technique may increase DVFS transition time, and still cannot guarantee minimal noise. In this work, we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization. Moreover, the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose. The results show that we are able to achieve minimal-noise sequence within desired transition time with 53% noise reduction and save more than 15–17% power compared with the traditional approach.","PeriodicalId":6491,"journal":{"name":"2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)","volume":"235 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87083034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators 基于fpga硬件加速器的区域优化低延迟近似乘法器

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3195996

Salim Ullah, Semeen Rehman, B. Prabakaran, F. Kriebel, Muhammad Abdullah Hanif, M. Shafique, Akash Kumar

{"title":"Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators","authors":"Salim Ullah, Semeen Rehman, B. Prabakaran, F. Kriebel, Muhammad Abdullah Hanif, M. Shafique, Akash Kumar","doi":"10.1145/3195970.3195996","DOIUrl":"https://doi.org/10.1145/3195970.3195996","url":null,"abstract":"The architectural differences between ASICs and FPGAs limit the effective performance gains achievable by the application of ASIC-based approximation principles for FPGA-based reconfigurable computing systems. This paper presents a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library. Our designs provide higher area, latency and energy gains along with better output accuracy than those offered by the state-of-the-art ASIC-based approximate multipliers. Moreover, compared to the multiplier IP offered by the Xilinx Vivado, our proposed design achieves up to 30%, 53%, and 67% gains in terms of area, latency, and energy, respectively, while incurring an insignificant accuracy loss (on average, below 1% average relative error). Our library of approximate multipliers is open-source and available online at https://cfaed.tudresden.de/pd-downloads to fuel further research and development in this area, and thereby enabling a new research direction for the FPGA community.","PeriodicalId":6491,"journal":{"name":"2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)","volume":"36 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80863855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 54

Long Live TIME: Improving Lifetime for Training-In-Memory Engines by Structured Gradient Sparsification 长寿命时间:通过结构化梯度稀疏化提高记忆中训练引擎的寿命

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Pub Date : 2018-06-01 DOI: 10.1145/3195970.3196071

Yi Cai, Yujun Lin, Lixue Xia, Xiaoming Chen, Song Han, Yu Wang, Huazhong Yang

引用次数: 36