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2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)最新文献

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Complete characterization of channel independent general DMT systems with cyclic prefix 具有循环前缀的信道无关的一般DMT系统的完整表征
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1329600
S. Dasgupta, A. Pandharipande
{"title":"Complete characterization of channel independent general DMT systems with cyclic prefix","authors":"S. Dasgupta, A. Pandharipande","doi":"10.1109/ISCAS.2004.1329600","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329600","url":null,"abstract":"The following fact is well known about discrete multitone transmission (DMT) systems: in the special case of orthogonal frequency division multiplexing (OFDM) when the input and output transforms are the IDFT and DFT matrices respectively, and the length of cyclic prefix is longer than the channel length. ISI free transmission is possible for almost all channel parameter values. In this paper, we ask whether more general DMT systems with cyclic prefix enjoy similar channel resistance? We show that among all possible FIR transmitting and receiving filters, of arbitrary order, channel resistant ISI free transmission requires (a) that the receive filter be matched to the transmit filters, and (b) that to within a scaling and delay, the transmit and receive filters it must have IDFT and DFT coefficients. Thus we prove that, should cyclic prefix be applied, then trivial variations of OFDM are the only channel resistant DMT system.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"41 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74483424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A closed loop transcutaneous power transfer system for implantable devices with enhanced stability 一种用于增强稳定性的植入式装置的闭环经皮功率传输系统
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328929
Guoxing Wang, Wentai Liu, R. Bashirullah, M. Sivaprakasam, G. Kendir, Ying Ji, M. Humayun, J. Weiland
{"title":"A closed loop transcutaneous power transfer system for implantable devices with enhanced stability","authors":"Guoxing Wang, Wentai Liu, R. Bashirullah, M. Sivaprakasam, G. Kendir, Ying Ji, M. Humayun, J. Weiland","doi":"10.1109/ISCAS.2004.1328929","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328929","url":null,"abstract":"This paper describes a closed-loop wireless inductive power transfer system for an implantable retinal prosthetic device. The proposed system is designed to ensure optimal power transfer to the implanted unit despite coil displacements and changes in load current while minimizing the sensitivity to component and process variation. Based on the system modeling, stability constraints are identified and applied to the feedback control system. The model is crucial in determining component values, circuit topology and number of transmitted bits per sampling period required to ensure system stability. In addition, the model significantly reduces design iterations compounded by lengthy circuit simulation. The model is verified by Matlab and SPICE level simulations. The critical analog circuits of the control system have been designed and fabricated through AMI 1.6 /spl mu/m process.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"67 1","pages":"IV-17"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74599195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques 利用约简技术计算非线性电路周期响应的大变化灵敏度
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1329530
P. Pai, E. Gad, R. Achar, R. Khazaka, M. Nakhla
{"title":"Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques","authors":"P. Pai, E. Gad, R. Achar, R. Khazaka, M. Nakhla","doi":"10.1109/ISCAS.2004.1329530","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329530","url":null,"abstract":"This work presents a new technique for computing large-change sensitivity (LCS) of steady-state operating point in nonlinear circuits. The basic idea underlying the algorithm is the construction of a reduced system of nonlinear equations that preserves the derivatives of steady-state response with respect to the desired network parameters. Large change variations are then obtained by solving the reduced systems instead of the original one.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"365 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74608388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.5 milliwatt SOS CMOS receiver for optical interconnect 用于光互连的2.5毫瓦SOS CMOS接收器
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1329731
A. Apsel, Zhongtao Fu
{"title":"A 2.5 milliwatt SOS CMOS receiver for optical interconnect","authors":"A. Apsel, Zhongtao Fu","doi":"10.1109/ISCAS.2004.1329731","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329731","url":null,"abstract":"We demonstrate a low power, high bit rate, cross coupled differential receiver in silicon on sapphire (SOS) CMOS to be used as part of an inter-chip optical interconnect. The internal amplifier of the transimpedance first stage provides high gain without requiring large, capacitive input gates. The resulting transimpedance stage extends the bandwidth of the differential receiver when small photodetectors are used. We fabricate this receiver in an SOS CMOS process to simplify the packaging of chip-to-chip interconnects with CMOS processors. The total measured power consumption of this receiver is 2.5 mW at gigabit rates, in a 0.5 /spl mu/m UTSi/spl trade/ SOS CMOS process.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"29 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74888609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Logically reversible arithmetic circuit using pass-transistor 逻辑可逆的算术电路使用通晶体管
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1329406
T. Hisakado, Hiroyoshi Iketo, K. Okumura
{"title":"Logically reversible arithmetic circuit using pass-transistor","authors":"T. Hisakado, Hiroyoshi Iketo, K. Okumura","doi":"10.1109/ISCAS.2004.1329406","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329406","url":null,"abstract":"This paper proposes novel reversible logic circuits, i.e., a reversible ExOR gate and a two-way AND gate. The gates operate in both directions and the input and output are indistinguishable. We design the circuits using dual-line pass-transistor logic. Applying the method to arithmetic circuits, we realize logically reversible arithmetic circuits. Because proposed circuits have no garbage output, the adder and multiplier operate as the subtracter and divider respectively by replacing the input with the output. We confirm the behavior of the circuits by both real experiments and SPICE simulations.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"9 1","pages":"II-853"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72960872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Accelerating MUSIC method on reconfigurable hardware for source localisation 加速MUSIC方法在可重构硬件上的源代码定位
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328760
A. Ahmedsaid, A. Amira, A. Bouridane
{"title":"Accelerating MUSIC method on reconfigurable hardware for source localisation","authors":"A. Ahmedsaid, A. Amira, A. Bouridane","doi":"10.1109/ISCAS.2004.1328760","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328760","url":null,"abstract":"This paper presents an implementation of the high resolution source localisation method MUSIC on an FPGA system. This method exploits the eigenvalue decomposition (EVD) of the correlation matrix generated from the signals received at different sensors. An efficient architecture for the computation of the singular value decomposition (SVD) and the EVD based on the Brent, Luk, Van loan (BLV) systolic array has been proposed. The architecture is three times more efficient and faster than the existing BLV structure. An optimised implementation has been efficiently carried out on the PPRC1000 board using a high level language for hardware design \"Handel-C\".","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"245 1","pages":"III-369"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73185979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
High density VLSI implementation of a bipolar CNN with reduced programmability 具有低可编程性的双极CNN的高密度VLSI实现
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328673
A. Paasio, J. Flak, M. Laiho, K. Halonen
{"title":"High density VLSI implementation of a bipolar CNN with reduced programmability","authors":"A. Paasio, J. Flak, M. Laiho, K. Halonen","doi":"10.1109/ISCAS.2004.1328673","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328673","url":null,"abstract":"In this paper a VLSI implementation of a bipolar CNN with a reduced programmability is described. The programmability of the weights and the bias term is reduced to one bit. Since the programming is digital, the template write time is fast. While losing some generality in the programming, the cell array is still able to perform most of the bipolar CNN templates presented so far. The proposed structure yields a very compact realization in a dense layout. The cell size using a 0.18/spl mu/m digital CMOS process was 155/spl mu/m/sup 2/.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"10 1","pages":"III-21"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73219439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low power flexible Rake receivers for WCDMA 用于WCDMA的低功耗柔性Rake接收机
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328949
B. Andreev, E. Titlebaum, E. Friedman
{"title":"Low power flexible Rake receivers for WCDMA","authors":"B. Andreev, E. Titlebaum, E. Friedman","doi":"10.1109/ISCAS.2004.1328949","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328949","url":null,"abstract":"Two low power flexible Rake receiver architectures are presented. The first architecture exploits the statistical distribution of multipath delays in wireless channels to reduce power dissipation. The second Rake architecture is based on a tradeoff between algorithm accuracy and circuit complexity. By introducing a negligible performance degradation, the SRAM memory for the input sample buffer is eliminated, achieving low power consumption and small silicon area. Both Rake architectures are targeted for third generation WCDMA mobile terminals (downlink receivers), but the circuits can also be applied to base station (uplink) receivers. The architectures have been synthesized in a 0.18 /spl mu/m standard cell CMOS technology using Cadence BuildGates. The proposed architectures achieve significant area and power savings as compared to previous circuits described in the literature.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"133 1","pages":"IV-97"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73248532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Adaptive multimedia content personalization 自适应多媒体内容个性化
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1329240
N. Doulamis, P. Georgilakis
{"title":"Adaptive multimedia content personalization","authors":"N. Doulamis, P. Georgilakis","doi":"10.1109/ISCAS.2004.1329240","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329240","url":null,"abstract":"Modeling multimedia content by identifying semantically meaningful entities can be arduous because it is difficult to simulate human perception. However, by creating an algorithm to respond interactively to user preference, content-retrieval systems can become more efficient and easier to use. In this paper, we investigate adaptive relevance feedback algorithms for interactive multimedia content personalization. In particular two interesting scenarios are examined. The first uses a weighted cross correlation similarity measure for ranking multimedia data. The second exploits concepts of functional analysis to model the similarity measure as a non-linear function, the type of which is estimated by the users' preferences. The algorithms are computationally efficient and they can be recursively implemented.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"133 1","pages":"II-189"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73252231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An on-off temporal filter circuit for visual motion analysis 一种用于视觉运动分析的开关时间滤波电路
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI: 10.1109/ISCAS.2004.1328689
Bertram E. Shi, Eric K. C. Tsang, Ph Au
{"title":"An on-off temporal filter circuit for visual motion analysis","authors":"Bertram E. Shi, Eric K. C. Tsang, Ph Au","doi":"10.1109/ISCAS.2004.1328689","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328689","url":null,"abstract":"We describe a temporal filtering circuit, which when cascaded with a previously reported chip for spatial filtering, implements the spatio-temporal filters required to construct motion energy filters, which have been used to model the functional characteristics of direction and speed tuned neurons in the primary visual cortex. To facilitate the combination, the temporal filter circuit uses the same on-off signal representation used by the spatial filtering chip. We present measurements results from a filter fabricated in a 1.5/spl mu/m CMOS n-well process that demonstrates that both the center frequency of the filter, which determines the tuned velocity bandwidth, can be tuned by adjusting external bias voltages. The filter can be tuned to bandwidths and center frequencies on the order of tens of Hertz, comparable to those measured in cortical neurons.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"235 1","pages":"III-85"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75733594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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