{"title":"具有低可编程性的双极CNN的高密度VLSI实现","authors":"A. Paasio, J. Flak, M. Laiho, K. Halonen","doi":"10.1109/ISCAS.2004.1328673","DOIUrl":null,"url":null,"abstract":"In this paper a VLSI implementation of a bipolar CNN with a reduced programmability is described. The programmability of the weights and the bias term is reduced to one bit. Since the programming is digital, the template write time is fast. While losing some generality in the programming, the cell array is still able to perform most of the bipolar CNN templates presented so far. The proposed structure yields a very compact realization in a dense layout. The cell size using a 0.18/spl mu/m digital CMOS process was 155/spl mu/m/sup 2/.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"10 1","pages":"III-21"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"High density VLSI implementation of a bipolar CNN with reduced programmability\",\"authors\":\"A. Paasio, J. Flak, M. Laiho, K. Halonen\",\"doi\":\"10.1109/ISCAS.2004.1328673\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a VLSI implementation of a bipolar CNN with a reduced programmability is described. The programmability of the weights and the bias term is reduced to one bit. Since the programming is digital, the template write time is fast. While losing some generality in the programming, the cell array is still able to perform most of the bipolar CNN templates presented so far. The proposed structure yields a very compact realization in a dense layout. The cell size using a 0.18/spl mu/m digital CMOS process was 155/spl mu/m/sup 2/.\",\"PeriodicalId\":6445,\"journal\":{\"name\":\"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)\",\"volume\":\"10 1\",\"pages\":\"III-21\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2004.1328673\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2004.1328673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High density VLSI implementation of a bipolar CNN with reduced programmability
In this paper a VLSI implementation of a bipolar CNN with a reduced programmability is described. The programmability of the weights and the bias term is reduced to one bit. Since the programming is digital, the template write time is fast. While losing some generality in the programming, the cell array is still able to perform most of the bipolar CNN templates presented so far. The proposed structure yields a very compact realization in a dense layout. The cell size using a 0.18/spl mu/m digital CMOS process was 155/spl mu/m/sup 2/.