2010 IEEE International Solid-State Circuits Conference - (ISSCC)最新文献

{"title":"A 477mW NoC-based digital baseband for MIMO 4G SDR","authors":"F. Clermidy, C. Bernard, R. Lemaire, Jérôme Martin, I. Panades, Y. Thonnart, P. Vivet, N. Wehn","doi":"10.1109/ISSCC.2010.5433920","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433920","url":null,"abstract":"Baseband processing for advanced Telecom applications have to face two contradictory issues [1]. The first one is the flexibility required, with the exploding number of modes for a single protocol (e.g. 63 for 3GPP-LTE), the number of protocols to be supported by a single chip (≫10 in 2010) and new applications requiring a handover between protocols. The second concern is related to performance and power consumption: performance demands are exploding (up to 100GOPS are now required) with decreasing power consumption constraints (roughly 500mW).","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"628 1","pages":"278-279"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78976906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit","authors":"M. Meterelliyoz, A. Goel, J. Kulkarni, K. Roy","doi":"10.1109/ISSCC.2010.5433991","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433991","url":null,"abstract":"Accurate and fast measurement and characterization of random threshold voltage (Vth) fluctuations is crucial in process optimization and yield learning, particularly for matching critical transistors such as SRAMs, sense amplifiers, differential amplifiers, etc. Traditional methods in which multiplexed devices under test (DUTs) are characterized using accurate current measurements require extensive data analysis [1–3]. A sense-amplifier based measurement method presented in [4] provides limited statistical data since it can measure the mismatch between only two devices. Recently, a digital array based technique is proposed in [5] with limited sensitivity. Finally, a sub-threshold technique presented in [6] provides high sensitivity but lacks on-chip calibration. This paper presents a low voltage, high sensitivity random process variations sensor utilizing an on-chip calibration circuit for improved accuracy. Moreover, the proposed sensor features a replica bias circuit which compensates global process-voltage-temperature (PVT) variations and maintains sensitivity for robust operation.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"22 1","pages":"186-187"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72680324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation","authors":"Marco Zanuso, S. Levantino, C. Samori, A. Lacaita","doi":"10.1109/ISSCC.2010.5433842","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433842","url":null,"abstract":"Digital Fractional-N PLLs allows easy cancellation of ΔΣ quantization noise and spurs [1], [2]. However, the actual results depend dramatically on the linearity of the time-to-digital converter (TDC). This paper presents a 3MHz bandwidth fractional-N synthesizer, which combines a 4ps TDC with digital linearization algorithm and a feedback phase interpolator with mismatch cancellation algorithm. In contrast to other TDC linearization approaches [3], this structure allows multiplier-free computations, fast and accurate spur cancellation, as well as digital post-cancellation of phase errors induced by the phase interpolator mismatches, avoiding more complex calibration loops [4].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"3 6 1","pages":"476-477"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88329696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 40nm 16-core 128-thread CMT SPARC SoC processor","authors":"Jinuk Luke Shin, K. Tam, Dawei Huang, B. Petrick, H. Pham, C. Hwang, H. Li, Alan P. Smith, Timothy Johnson, F. Schumacher, D. Greenhill, A. Leon, Allan Strong","doi":"10.1109/ISSCC.2010.5434030","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434030","url":null,"abstract":"This next generation of Chip Multithreaded (CMT) SPARC SoC processor, code named Rainbow Falls, doubles on-chip thread count over its predecessor the UltraSparc T2+. The chip offers high levels of integration and scalability with twice the number of cores, a larger L2 cache, and higher maximum I/O bandwidth, within the same power envelope. Sixteen 8-threaded enhanced SPARC cores (SPC) provide 128 threads in a single die, delivering the highest thread count for a general-purpose microprocessor. The new cache coherency further allows up to 4-way glueless systems with a total of 512 threads. Each core communicates with the unified 6MB L2 cache through a crossbar (CCX) delivering 461GB/s (Fig. 5.2.1). A gasket (CXG) is also introduced to manage the congestion and synchronization of the massive interconnect between the 16 cores and the crossbar. This facilitates a synchronized delay control between any core and any L2 bank for partial core product binning and testing.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"54 22","pages":"98-99"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91464924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis control","authors":"Chen Zheng, D. Ma","doi":"10.1109/ISSCC.2010.5433986","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433986","url":null,"abstract":"Nowadays switching DC-DC converters have become indispensable in power-efficient VLSI systems. As operation frequency increases, load fluctuations in such a device require high switching frequencies in DC-DC converters for fast transient response. Meanwhile, as the switching frequency, fs, increases, sizes of inductors (Ls) and capacitors (Cs) decrease with fs, allowing the use of smaller off-chip or even on-chip Ls and Cs. This not only reduces cost and space, but also allows a larger or better battery to be used, which in turn, improves the system run-time and performance. However, as fs increases, power loss at the power stage will increase roughly with √fs [1]. The efficiency is thus sacrificed for high-frequency operations. For example, for a converter that achieves 90% efficiency at 1MHz, when fs is increased to 10 MHz, power loss goes up by √10 times, causing the efficiency to drop below 70% [1]. On the other hand, as semiconductor industry is facing unprecedented power crisis, numerous power-management techniques have been recently developed. One major technique is called dynamic voltage scaling (DVS), in which a variable-output DC-DC converter is usually adopted to adjust supply voltage and operation frequency, based on instantaneous workload. Buck converter topology has been widely used for these applications. However, because a non-inverting flyback converter can achieve both step-up and step-down conversions, such a structure is more desirable in DVS-based applications to maximize power saving with a wider supply range [2]. However, compared to buck or boost converters, a non-inverting flyback converter requires two additional switches. As a result, both switching and conduction loss are doubled. Furthermore, the converter efficiency is greatly degraded (as shown in Fig. 10.5.1). However, it exhibits an obvious advantage when Vout is close to Vg, where the buck or boost converter experiences a sharp increase in power loss. In addition, as the duty ratio approaches 100%, the discharge (charge) period for a buck (boost) converter becomes extremely short, forcing the inductor to be charged at a much higher current level. It thus leads to significant power loss and switching noise, and imposes severe design constraints on the transient responses of the controller and buffers.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"35 1","pages":"204-205"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87151449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ES6: Can we rebuild them? bionics beyond 2010","authors":"Maysam Ghovanloo, T. Denison","doi":"10.1109/ISSCC.2010.5433873","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433873","url":null,"abstract":"The terms “bionics” and “neuroprosthesis” understandably capture the engineers' imagination. Oftentimes, however, this fascination results more from science fiction than actual facts on the reality of unmet clinical needs and the real technical issues of designing a bionic system. Yet not all work in this field is sci-fi, and engineers working with clinical researchers and scientists have realized several milestones in the treatment of chronic diseases. Perhaps the most successful example of a bionic system is the cochlear prosthesis, which has helped restore a measure of hearing in over 150,000 patients, so far. Another active field is neuromodulation, where neurostimulators targeting specific neural circuits are being applied as a therapy for a variety of diseases including Parkinson's disease, incontinence, and obsessive compulsive disorder. Clearly, in the proper context, interfacing silicon circuits to the patients' neural circuits may achieve profound effects.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"17 1","pages":"532-533"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87565876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC","authors":"","doi":"10.1109/ISSCC.2010.5434050","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434050","url":null,"abstract":"EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"22 1","pages":"58-59"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73353349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 2Gb/s network processor with a 24mW IPsec offload for residential gateways","authors":"Y. Nishida, K. Kawai, K. Koike","doi":"10.1109/ISSCC.2010.5433917","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433917","url":null,"abstract":"The Internet has become an important tool to deliver services such as Voice over Internet Protocol (IP) and high-definition video. To enable the widespread use of these services, it is essential to ensure quality-of-service (QoS) and security protection in communication. In using consumer-oriented gateway equipment (GW) consisting of low-cost network processors (NPs), however, it is difficult to ensure QoS because the CPU load becomes 100% when packets are received at a traffic load of 1Gb/s. A packet engine (PE) achieving a throughput of 2Gb/s (i.e., bidirectional 1Gb/s communication) and offloading the network processing from CPUs solves the problem as shown in Fig. 15.4.1. The PE achieves a 2Gb/s throughput for all cases as shown in Fig. 15.4.2 as follows: (1) inline-type IPsec circuits whose transmitting/receiving blocks independently process enc/decryption, authentication, and encapsulation [1] achieve a total processing speed of 2Gb/s; (2) an IP-forwarding performance of 2Gb/s is achieved by adopting a high-speed, compact look-up circuit [1] that searches by providing an action rule from one memory read-out circuit to multiple comparators in an IP switch (IP-SW); and (3) a local-area-network switch (LAN-SW) achieves 5Gb/s forwarding by 5 parallel look-up engines and a high-speed internal packet buffer.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"117 1","pages":"280-281"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73524606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM","authors":"N. Miura, Kazutaka Kasuga, Mitsuko Saito, T. Kuroda","doi":"10.1109/ISSCC.2010.5433909","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433909","url":null,"abstract":"This paper presents an 8Tb/s 1pJ/b 0.8mm2/Tb/s quad data rate (QDR) inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. The interface consists of 1024-bit parallel inductive-coupling transceivers operating at 8Gb/s/link. In the DRAM transceiver, data are multiplexed and demultiplexed by using a quadrature clock and XOR operation. This circuit technique for QDR compensates for transistor performance gap between the GPU and the DRAM to achieve 8Gb/s bandwidth. The clock for data retiming is recovered from the received data by using an injection-lock VCO. Clock links and clock distribution circuits are not needed, resulting in small layout area of 0.8mm2/Tb/s. Frontend of the transceiver is implemented using NMOS CML circuits with adaptive bias control. The transceiver's sensitivity to PVT variations is small, enabling all the 1024 parallel transceivers to operate at BER≪10{−16}. It also reduces the design margin required of the transceiver, resulting in power reduction to 1pJ/b. Compared to the latest wired 40nm DRAM interface [1], the bandwidth is 32x higher, while the energy consumption is 1/8 and the layout area is 1/22.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"63 1","pages":"436-437"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73413000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s","authors":"G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, Doyle Rivers, E. Sirizotti, F. Paolini, Giuliano Gennaro Imondi, G. Naso, G. Santin, L. Botticchio, L. D. Santis, L. Pilolli, M. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. D. Francesco, M. Goldman, C. Haid, D. D. Cicco, D. Orlandi, F. Rori, M. Rossini, T. Vali, R. Ghodsi, Frankie Roohparvar","doi":"10.1109/ISSCC.2010.5433949","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433949","url":null,"abstract":"In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm2.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"86 1","pages":"444-445"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74018710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}