A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis control

Chen Zheng, D. Ma
{"title":"A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis control","authors":"Chen Zheng, D. Ma","doi":"10.1109/ISSCC.2010.5433986","DOIUrl":null,"url":null,"abstract":"Nowadays switching DC-DC converters have become indispensable in power-efficient VLSI systems. As operation frequency increases, load fluctuations in such a device require high switching frequencies in DC-DC converters for fast transient response. Meanwhile, as the switching frequency, fs, increases, sizes of inductors (Ls) and capacitors (Cs) decrease with fs, allowing the use of smaller off-chip or even on-chip Ls and Cs. This not only reduces cost and space, but also allows a larger or better battery to be used, which in turn, improves the system run-time and performance. However, as fs increases, power loss at the power stage will increase roughly with √fs [1]. The efficiency is thus sacrificed for high-frequency operations. For example, for a converter that achieves 90% efficiency at 1MHz, when fs is increased to 10 MHz, power loss goes up by √10 times, causing the efficiency to drop below 70% [1]. On the other hand, as semiconductor industry is facing unprecedented power crisis, numerous power-management techniques have been recently developed. One major technique is called dynamic voltage scaling (DVS), in which a variable-output DC-DC converter is usually adopted to adjust supply voltage and operation frequency, based on instantaneous workload. Buck converter topology has been widely used for these applications. However, because a non-inverting flyback converter can achieve both step-up and step-down conversions, such a structure is more desirable in DVS-based applications to maximize power saving with a wider supply range [2]. However, compared to buck or boost converters, a non-inverting flyback converter requires two additional switches. As a result, both switching and conduction loss are doubled. Furthermore, the converter efficiency is greatly degraded (as shown in Fig. 10.5.1). However, it exhibits an obvious advantage when Vout is close to Vg, where the buck or boost converter experiences a sharp increase in power loss. In addition, as the duty ratio approaches 100%, the discharge (charge) period for a buck (boost) converter becomes extremely short, forcing the inductor to be charged at a much higher current level. It thus leads to significant power loss and switching noise, and imposes severe design constraints on the transient responses of the controller and buffers.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"39","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2010.5433986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 39

Abstract

Nowadays switching DC-DC converters have become indispensable in power-efficient VLSI systems. As operation frequency increases, load fluctuations in such a device require high switching frequencies in DC-DC converters for fast transient response. Meanwhile, as the switching frequency, fs, increases, sizes of inductors (Ls) and capacitors (Cs) decrease with fs, allowing the use of smaller off-chip or even on-chip Ls and Cs. This not only reduces cost and space, but also allows a larger or better battery to be used, which in turn, improves the system run-time and performance. However, as fs increases, power loss at the power stage will increase roughly with √fs [1]. The efficiency is thus sacrificed for high-frequency operations. For example, for a converter that achieves 90% efficiency at 1MHz, when fs is increased to 10 MHz, power loss goes up by √10 times, causing the efficiency to drop below 70% [1]. On the other hand, as semiconductor industry is facing unprecedented power crisis, numerous power-management techniques have been recently developed. One major technique is called dynamic voltage scaling (DVS), in which a variable-output DC-DC converter is usually adopted to adjust supply voltage and operation frequency, based on instantaneous workload. Buck converter topology has been widely used for these applications. However, because a non-inverting flyback converter can achieve both step-up and step-down conversions, such a structure is more desirable in DVS-based applications to maximize power saving with a wider supply range [2]. However, compared to buck or boost converters, a non-inverting flyback converter requires two additional switches. As a result, both switching and conduction loss are doubled. Furthermore, the converter efficiency is greatly degraded (as shown in Fig. 10.5.1). However, it exhibits an obvious advantage when Vout is close to Vg, where the buck or boost converter experiences a sharp increase in power loss. In addition, as the duty ratio approaches 100%, the discharge (charge) period for a buck (boost) converter becomes extremely short, forcing the inductor to be charged at a much higher current level. It thus leads to significant power loss and switching noise, and imposes severe design constraints on the transient responses of the controller and buffers.
具有自适应补偿单界迟滞控制的10MHz 92.1%效率绿模自动可重构开关变换器
如今,开关DC-DC转换器已成为高效节能VLSI系统中不可或缺的一部分。随着工作频率的增加,该器件的负载波动要求DC-DC变换器的开关频率高,以实现快速的瞬态响应。同时,随着开关频率fs的增加,电感(Ls)和电容(Cs)的尺寸随fs减小,从而允许使用更小的片外甚至片内Ls和Cs。这不仅降低了成本和空间,而且还允许使用更大或更好的电池,这反过来又提高了系统的运行时间和性能。然而,随着fs的增加,功率级的功率损耗将大致增加√fs[1]。因此,高频操作牺牲了效率。例如,对于一个在1MHz时效率达到90%的转换器,当fs增加到10mhz时,功率损失增加10倍,导致效率下降到70%以下。另一方面,由于半导体工业正面临前所未有的电力危机,近年来出现了许多电力管理技术。其中一种主要技术被称为动态电压缩放(DVS),该技术通常采用可变输出DC-DC变换器,根据瞬时工作负载来调节电源电压和工作频率。Buck变换器拓扑结构已广泛应用于这些应用中。然而,由于非反相反激变换器可以实现升压和降压转换,因此这种结构在基于dvs的应用中更可取,以便在更宽的供电范围内最大限度地节省功率。然而,与降压或升压变换器相比,非反相反激变换器需要两个额外的开关。因此,开关损耗和传导损耗都增加了一倍。此外,变流器效率也大大降低(如图10.5.1所示)。然而,当Vout接近Vg时,它表现出明显的优势,此时降压或升压转换器的功率损耗急剧增加。此外,当占空比接近100%时,降压(升压)变换器的放电(充电)周期变得非常短,迫使电感在更高的电流水平上充电。因此,它会导致显著的功率损耗和开关噪声,并对控制器和缓冲器的瞬态响应施加严格的设计约束。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信