2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems最新文献_第7页

Forward and backward guarding in early output logic 早期输出逻辑中的正向和反向保护

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012134

C. Brej, D. Edwards

引用次数: 8

Asynchronous two-level logic of reduced cost 降低成本的异步两级逻辑

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012101

I. Lemberski, P. Fiser

引用次数: 4

Comparison of different test strategies on a mixed-signal circuit 混合信号电路中不同测试策略的比较

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012090

J. Brenkus, V. Stopjaková, Ronny Vanhooren, A. Chichkov

引用次数: 0

Enhanced LEON3 core for superscalar processing 用于超标量处理的增强LEON3核心

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012137

Krzysztof Marcinek, A. W. Luczyk, W. Pleskacz

引用次数: 10

Case Study : A class E power amplifier for ISO-14443A 案例研究:符合ISO-14443A标准的E类功率放大器

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012091

E. D. Mulder, W. Aerts, B. Preneel, I. Verbauwhede, G. Vandenbosch

引用次数: 7

Ultra low-voltage switched current mirror 超低电压开关电流反射镜

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012138

Y. Berg, O. Mirmotahari

引用次数: 0

0.5V 160-MHz 260uW all digital phase-locked loop 0.5V 160mhz 260uW全数字锁相环

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012125

Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng

引用次数: 1

Optimization concepts for self-healing asynchronous circuits 自愈异步电路的优化概念

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012100

T. Panhofer, W. Friesenbichler, M. Delvai

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引用次数: 11

Improve clock gating through power-optimal enable function selection 通过功率优化使能功能选择改进时钟门控

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012094

Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou

{"title":"Improve clock gating through power-optimal enable function selection","authors":"Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou","doi":"10.1109/DDECS.2009.5012094","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012094","url":null,"abstract":"Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved. This paper presents a technique for improving clock gating by optimizing the enable functions. The problem of improving clock gating is formulated as finding the optimal set of enable functions in the shared logic cone that leads to best power reduction on flip flops. First, enable functions are identified by random simulation and SAT. Then the optimal set of enable functions is found with partition method. This paper demonstrates the effectiveness of the approach through testing on MCNC benchmarks and industrial circuits. The experimental results show that the algorithm will get as much power saving as 3 times of that of the original clock gating circuits, and all benchmarks can run in tens of seconds.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"12 1 1","pages":"30-33"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76906721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

An SOC platform for ADC test and measurement 一个用于ADC测试和测量的SOC平台

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012087

Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann

引用次数: 2