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2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems最新文献

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Test scheme for switched-capacitor circuits by digital analyses 开关电容电路的数字分析测试方案
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012113
Y. Wen
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引用次数: 1
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions 同时开关噪声条件下CMOS数字块的时序特性分析
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012119
F. Azaïs, Y. Bertrand, M. Renovell
{"title":"An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions","authors":"F. Azaïs, Y. Bertrand, M. Renovell","doi":"10.1109/DDECS.2009.5012119","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012119","url":null,"abstract":"This paper analyzes the impact of Simultaneous Switching Noise (SSN) on the timing behavior of CMOS digital blocks. The concept of Instantaneous Transfer Function is introduced to interpret noisy signals and perform timing measurements on such signals. It is shown that the average swing during switching is the key parameter to predict the noise impact on the delay of a logic path, whereas the peak of noise is not relevant. The influence of structural parameters such as the block topology is evaluated, and the unpredictable aspect of SSN impact on path delay is highlighted.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"13 1","pages":"158-163"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88879308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing 面向DRAM邻域模式敏感故障测试的物理设计
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012108
Yiorgos Sfikas, Y. Tsiatouhas
{"title":"Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing","authors":"Yiorgos Sfikas, Y. Tsiatouhas","doi":"10.1109/DDECS.2009.5012108","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012108","url":null,"abstract":"Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated with it, compared to other fault models, restricts its wide adoption for memory testing. In this work we exploit the physical design (layout) of folded DRAM memory arrays to introduce a new neighborhood type for NPSF testing and a pertinent test and locate algorithm. This algorithm reduces drastically the test application time (about 58% with respect to the well known Type-1 neighborhood) aiming to make the NPSF model also a cost attractive choice. In addition, we introduce the Neighborhood Word-Line Sensitive Fault model and the corresponding test algorithm to cover those faults along with NPSFs, achieving test application time cost reduction from 33% to 41%, depending on various assumptions, with respect to the Type-1 neighborhood.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"1 1","pages":"108-113"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82877964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Using 3-valued memory representation for state space reduction in embedded assembly code model checking 在嵌入式汇编代码模型检查中使用3值内存表示进行状态空间缩减
2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI: 10.1109/DDECS.2009.5012109
T. Reinbacher, M. Horauer, Bastian Schlich
{"title":"Using 3-valued memory representation for state space reduction in embedded assembly code model checking","authors":"T. Reinbacher, M. Horauer, Bastian Schlich","doi":"10.1109/DDECS.2009.5012109","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012109","url":null,"abstract":"Model checking of assembly code is a promising approach to satisfy the demand for verification in nowadays ultra-high reliable embedded systems software. Frequent interaction with its environment, e.g., by sending or reading data over the microcontrollers I/O lines, lies in the nature of embedded systems. Thus, making the long-standing problem of explicit-model checking even worse, namely the state-explosion problem. This paper presents a concept to tackle these difficulties by using a 3-valued logic in the state representation and showing its benefits in terms of state-space savings whenever logic operations are executed by the target microcontroller. To highlight the effectiveness of this approach, termed delayed nondeterminism with look ahead, an embedded program exemplifying typical microcontroller source code is analyzed and the resulting state space sizes are discussed. The introduced abstraction technique is implemented in the MCS-51 simulator component for the [mc]square model checker which is developed by the RWTH Aachen University.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"42 1","pages":"114-119"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87466307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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