0.5V 160mhz 260uW全数字锁相环

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems Pub Date : 2009-04-15 DOI:10.1109/DDECS.2009.5012125

Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng

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引用次数: 1

摘要

提出了一种0.13um CMOS工艺的低功耗全数字锁相环(ADPLL)。基于脉冲的数字控制振荡器(PB-DCO)具有高分辨率和宽量程。ADPLL的锁定时间小于32个参考时钟周期。乘数是2到63。在0.5V供电电压下，160mhz时功耗为260uW, 60mhz时功耗为80uW。

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0.5V 160-MHz 260uW all digital phase-locked loop

A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.

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2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

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