2007 25th International Conference on Computer Design最新文献_第2页

Bounded model checking of embedded software in wireless cognitive radio systems 无线认知无线电系统中嵌入式软件的有界模型检验

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601875

Nannan He, M. Hsiao

引用次数: 13

Combining cluster sampling with single pass methods for efficient sampling regimen design 将聚类抽样与单次抽样相结合，设计有效的抽样方案

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601941

Paul D. Bryan, T. Conte

{"title":"Combining cluster sampling with single pass methods for efficient sampling regimen design","authors":"Paul D. Bryan, T. Conte","doi":"10.1109/ICCD.2007.4601941","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601941","url":null,"abstract":"Microarchitectural simulation is orders of magnitude slower than native execution. As more elements are accurately modeled, problems associated with slow simulation are further exacerbated. Given these issues, many researchers have devised sampling techniques to reduce simulation time. When cluster sampling techniques are used, care must be taken to remove sampling and non-sampling biases. Researchers have devised clever methods for effectively reducing non-sampling bias, but little work has been proposed for efficient reduction of sampling bias (sampling regimen design). Traditionally, sampling regimen design has been an iterative process that required a full workload simulation for error comparison. In this study, a single-pass simulation technique for sampling regimen design is proposed. Using this method, thousands of sampling regimen candidates can be simultaneously evaluated. With this technique, simulation speed was increased by an average factor of 17 with a maximum increase of 73 times relative to the total workload simulation. Additionally, this technique allows the user to effectively estimate the sample error without running the entire workload.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"6 1","pages":"472-479"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91072438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Register binding guided by the size of variables 由变量大小引导的寄存器绑定

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601957

N. Chabini, W. Wolf

{"title":"Register binding guided by the size of variables","authors":"N. Chabini, W. Wolf","doi":"10.1109/ICCD.2007.4601957","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601957","url":null,"abstract":"An important problem is how to carry out register binding such that any register has to be bound to a set of variables such that the difference between their sizes is as small as possible. For the case of hardware implementations, satisfying this latter constraint will allow to reduce the complexity of the clock generation tree, and saving area occupied by the registers which is very important for the case of system-on-chip and some embedded systems. When registers are already built, satisfying this latter constraint would allow reducing power consumption due to useless switching activities that will happen into any register that is bound to variables with different sizes. Assuming that the size in bits of any variable is known, we propose in this paper exact algorithms to optimally solve this problem for the case of acyclic graphs. An extended version of this problem is how to solve it while controlling the number of variables to be assigned to a same register. We also propose exact algorithms to optimally solve this latter version of the problem. Experimental results are provided. We also test the impact of the proposed approach in the case of a hardware implementation using the design analyzer tool from Synopsys Inc.. Obtained results have shown that both area and power consumption have been reduced.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"31 1","pages":"587-594"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90108705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The challenge in testing MIMO in a Wi-Fi or WiMAX context 在Wi-Fi或WiMAX环境下测试MIMO的挑战

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601904

K. Vandrup

引用次数: 0

Hardware design of a Binary Integer Decimal-based floating-point adder 基于二进制整数十进制的浮点加法器的硬件设计

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601915

C. Tsen, S. González-Navarro, M. Schulte

{"title":"Hardware design of a Binary Integer Decimal-based floating-point adder","authors":"C. Tsen, S. González-Navarro, M. Schulte","doi":"10.1109/ICCD.2007.4601915","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601915","url":null,"abstract":"Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the binary integer decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70% of the BID adderpsilas area is due the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hardware for other DFP operations. To our knowledge, this is the first hardware design for adding and subtracting IEEE P754 BID-encoded DFP numbers.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"18 1","pages":"288-295"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78400419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Circuit-level mismatch modelling and yield optimization for CMOS analog circuits CMOS模拟电路的电路级失配建模和良率优化

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601948

Mingjing Chen, A. Orailoglu

引用次数: 1

Analytical thermal placement for VLSI lifetime improvement and minimum performance variation 分析热安置VLSI寿命改善和最小的性能变化

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601882

A. Kahng, S. Kang, Wei Li, Bao Liu

引用次数: 5

Digital calibration of RF transceivers for I-Q imbalances and nonlinearity 射频收发器I-Q不平衡和非线性的数字校准

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601946

E. Acar, S. Ozev

引用次数: 13

Statistical timing analysis using Kernel smoothing 使用核平滑的统计时序分析

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601886

J. Wong, A. Davoodi, Vishal Khandelwal, Ankur Srivastava, M. Potkonjak

引用次数: 2

Modeling soft error effects considering process variations 考虑工艺变化的软误差影响建模

2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601927

Chong Zhao, S. Dey

引用次数: 4