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Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor 微处理器功能单元硬延迟故障的低成本运行时诊断
2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601919
S. Ozev, Daniel J. Sorin, Mahmut Yilmaz
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引用次数: 6
Priority-monotonic energy management for real-time systems with reliability requirements 具有可靠性要求的实时系统的优先单调能量管理
2007 25th International Conference on Computer Design Pub Date : 2007-10-01 DOI: 10.1109/ICCD.2007.4601963
Dakai Zhu, Xuan Qi, Hakan Aydin
{"title":"Priority-monotonic energy management for real-time systems with reliability requirements","authors":"Dakai Zhu, Xuan Qi, Hakan Aydin","doi":"10.1109/ICCD.2007.4601963","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601963","url":null,"abstract":"Considering the impact of the popular energy management technique Dynamic Voltage and Frequency Scaling (DVFS) on system reliability, the Reliability-Aware Power Management (RA-PM) problem has been recently explored to save energy while maintaining system reliability. In this work, focusing on Rate Monotonic Scheduling (RMS) policy, we study static RA-PM schemes for periodic realtime tasks. After showing the intractability of the problem, we focus on two widely-known feasibility tests for RMS (namely, the Liu-Layland bound and Time Demand Analysis) and propose a number of heuristics based on the priority-monotonic speed assignment. The heuristics are evaluated through extensive simulations.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"38 1","pages":"629-635"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86505763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Speed-area optimized FPGA implementation for Full Search Block Matching 全搜索块匹配的速度区域优化FPGA实现
2007 25th International Conference on Computer Design Pub Date : 2007-01-01 DOI: 10.1109/ICCD.2007.4601874
Santosh K. Ghosh, A. Saha
{"title":"Speed-area optimized FPGA implementation for Full Search Block Matching","authors":"Santosh K. Ghosh, A. Saha","doi":"10.1109/ICCD.2007.4601874","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601874","url":null,"abstract":"This paper presents an FPGA based hardware design for full search block matching (FSBM) based motion estimation (ME) in video compression. The significantly higher resolution of HDTV based applications is achieved by using FSBM based ME. The proposed architecture uses a modification of the sum-of-absolute-differences (SAD) computation in FSBM such that the total number of additions/subtraction operations is drastically reduced. This successfully optimizes the conflicting design requirements of high throughput and small silicon area. Comparison results demonstrate the superior performance of our architecture. Finally, the design of a reconfigurable block matching hardware has been discussed.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"22 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2007-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81233345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Increased CPU speed drives changes in multiprocessor cache and bus designs 增加的CPU速度驱动多处理器缓存和总线设计的变化
2007 25th International Conference on Computer Design Pub Date : 1987-06-15 DOI: 10.5555/26514.26519
Wilsonb
{"title":"Increased CPU speed drives changes in multiprocessor cache and bus designs","authors":"Wilsonb","doi":"10.5555/26514.26519","DOIUrl":"https://doi.org/10.5555/26514.26519","url":null,"abstract":"","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"18 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"1987-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78371061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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