IEEE Transactions on Components and Packaging Technologies最新文献

{"title":"Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits","authors":"Ankur Jain, Robert E. Jones, R. Chatterjee, S. Pozder","doi":"10.1109/TCAPT.2009.2020916","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2020916","url":null,"abstract":"Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a significant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"56-63"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2020916","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Capacitive Pressure Sensor With Very Large Dynamic Range","authors":"E. Bakhoum, M. Cheng","doi":"10.1109/TCAPT.2009.2022949","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2022949","url":null,"abstract":"A new capacitive pressure sensor with very large dynamic range is introduced. The sensor is based on a new technique for substantially changing the surface area of the electrodes, rather than the inter-electrode spacing as commonly done at the present. The prototype device has demonstrated a change in capacitance of approximately 2500 pF over a pressure range of 10 kPa.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"79-83"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2022949","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of Piezoelectric Oscillating Fan-Cooled Heat Sinks for Electronics Cooling","authors":"J. Petroski, M. Arik, M. Gursoy","doi":"10.1109/TCAPT.2009.2023859","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2023859","url":null,"abstract":"Piezoelectric fans have been investigated for electronics cooling over the last decade. The primary usage or method has been to place the vibrating fan near the surface to be cooled. The piezofan used in the current study is composed of a piezo actuator attached to a flexible metal beam. It is operated at up to 120-VAC and at 60 Hz. While most of the research in the literature focused on cooling bare surfaces, larger heat transfer rates are of interest in the present study. A system of piezoelectric fans and a heat sink is presented as a more efficient method of system cooling with these fans. In this paper, a heat sink and piezoelectric fan system demonstrated a cooling capability of 1 C/W over an area of about 75 cm2 where electronic assemblies can be mounted. The heat sink not only provides surface area, but also flow shaping for the unusual 3-D flow field of the fans. A volumetric coefficient of performance (COPv) is proposed, which allows a piezofan and heat sink system volume to be compared against the heat dissipating capacity of a similar heat sink of the same volume for natural convection. A piezofan system is shown to have a COPv of five times that of a typical natural-convection solution. The paper will further discuss the effect of nozzles in flow shaping obtained via experimental and computational studies. A 3-D flow field of the proposed cooling scheme with a piezofan is obtained via a flow visualization method. Velocities at the heat sink in the order of 1.5 m/s were achieved through this critical shaping. Finally, the overall system characterization to different heat loads and fan amplitudes will be discussed.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"25-31"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2023859","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area $({>}100~{rm mm}^{2})$ Chips","authors":"T. Lei, J. Calata, G. Lu, Xu Chen, S. Luo","doi":"10.1109/TCAPT.2009.2021256","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2021256","url":null,"abstract":"A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm2) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125°C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275°C with the sintered joints having the melting temperature of silver at 961°C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"98-104"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2021256","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of ACF Interconnections on FR-4 Substrates","authors":"L. Frisk, K. Saarinen, Anne Cumini","doi":"10.1109/TCAPT.2009.2026570","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2026570","url":null,"abstract":"The use of anisotropic conductive adhesives (ACA) in flip chip interconnection technology has become very popular because of their numerous advantages. The ACA process can be used in high-density applications and with various substrates as the bonding temperature is lower than that in the soldering process. In this paper, six test lots were assembled using two anisotropic conductive adhesive films (ACF) and four different FR-4 substrates. FR-4 was chosen as it is an interesting alternative for making low-cost high-density interconnections. Some of the chips were thinned to study the effect on reliability. To study the effect of bonding pressure, four different pressures were used in every test lot. The reliability of the assembled test samples was studied in a temperature cycling test carried out between temperatures of -40°C and 125°C for 10 000 cycles. A finite element model (FEM) was used to study the shear stresses in the interconnections during the test. Marked differences between the substrates were seen. The substrate thinning and also the chip thinning increased the reliability of the test samples. From the FEM, it was seen that both decreased the shear stress in the adhesive, which is assumed to be the reason for the increased reliability. A significant difference was seen in the reliability between the ACFs. This was probably caused by differences in the conductive particle materials and the T g values and of the ACFs. In addition, the bump material used with the ACFs varied, which most likely affected the reliability of the test samples.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"138-147"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2026570","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of 3-D Silicon Module With TSV for System in Packaging","authors":"N. Khan, V. S. Rao, S. Lim, H. We, V. Lee, Xiaowu Zhang, E. Liao, R. Nagarajan, T. Chai, V. Kripesh, J. Lau","doi":"10.1109/TCAPT.2009.2037608","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2037608","url":null,"abstract":"Portable electronic products demand multifunctional module comprising of digital, radio frequency and memory functions. Through silicon via (TSV) technology provides a means of implementing complex, multifunctional integration with a higher packing density for a system in package. A 3-D silicon module with TSV has been developed in this paper. Thermo-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the barrier copper via is exposed by the backgrinding process. A two-stack silicon module is developed and module fabrication details are given in this paper. The module reliability has been evaluated under temperature cycling (-40/125°C ) and drop test.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"3-9"},"PeriodicalIF":0.0,"publicationDate":"2010-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2037608","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direct Submount Cooling of High-Power LEDs","authors":"D. Kim, E. Rahim, A. Bar-Cohen, B. Han","doi":"10.1109/TCAPT.2010.2040618","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2040618","url":null,"abstract":"Rapidly increasing light emitting diode (LED) heat fluxes necessitate the development of aggressive thermal management techniques that can intercept the dissipated heat directly in the submount. Microgap coolers, which eliminate solid-solid thermal interface resistance and provide direct contact between chemically inert, dielectric fluids and the back surface of an active electronic component, offer a most promising approach for cooling high-power LEDs. This paper focuses on the two-phase thermofluid characteristics of a dielectric liquid, FC-72, flowing in an asymmetrically heated chip-scale microgap channel, 10 mm wide × 37 mm long, with channel heights varying from 110 μm to 500 μm and channel wall heat fluxes of 200 kW/m2. The experimental two-phase, area-averaged heat transfer coefficients of FC-72 reached 10 kW/m2·K, significantly higher than the single-phase FC-72 values, thus providing cooling capability in the range associated with water under forced convection. Data obtained for single-phase water yielded very good agreement with predictions for the convective heat transfer coefficients and served to validate the accuracy of the experimental apparatus and measurement technique. It is shown that this two-phase cooling approach could be used to dissipate in excess of 600 kW/m2 in the submount of high-power LEDs.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"698-712"},"PeriodicalIF":0.0,"publicationDate":"2010-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2040618","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Measurement of the Hygroscopic Swelling Coefficient of Thin Film Polymers Used in Semiconductor Packaging","authors":"C. Jang, Samson Yoon, B. Han","doi":"10.1109/TCAPT.2009.2038366","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2038366","url":null,"abstract":"An advanced method based on the digital image correlation technique is implemented for characterization of hygroscopic swelling of thin film polymers. The accuracy of the proposed method is experimentally validated through a comparison with the well-established Moiré interferometry technique. It is applied to various thin film polymers, including polyimide, solder resist, anisotropic conductive film, and thin woven glass/resin composite. The magnitude of hygroscopic swelling coefficients ranges from 0.067 to 0.25%strain/%wt for those films. A practical guideline for specimen preparation and experimental setup is provided for proper implementation of the proposed method.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"340-346"},"PeriodicalIF":0.0,"publicationDate":"2010-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2038366","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Coupled Thermal-Stress Analysis for FC-BGA Packaging Reliability Design","authors":"K. Hirohata, K. Hisano, M. Mukai, H. Aoki, C. Takubo, T. Kawakami, M. Pecht","doi":"10.1115/IMECE2006-13800","DOIUrl":"https://doi.org/10.1115/IMECE2006-13800","url":null,"abstract":"In order to improve electronics packaging design, it is important to evaluate the cooling performance and reliability of the electronics packaging structure of a product. To that end, it is necessary to predict the temperature, deformation, and stress distributions of the package under field conditions. In the case of a packaging structure comprising a flip-chip ball grid array package, a heat spreader, thermal grease, a cooling structure, solder joints, and a motherboard, an increase in the contact thermal resistance may occur, depending on the interface contact condition between the cooling structure and the heat-spreader due to the thermal deformation of the package. Contact thermal resistance problems involve the interactive relationship of the thermal and stress distributions. A coupled thermal-stress analysis, with consideration of the time-space variation of contact thermal resistance, was conducted to duplicate the behavior of temperature, deformation, and stress distributions of a flip-chip ball grid array package under field conditions. It was found that: 1) the average contact thermal resistance across the interface between the heat-spreader and the plate fin, which was predicted by the coupled thermal-stress analysis, increased compared to the average contact thermal resistance in the case of uniform contact pressure, and 2) the contact thermal resistance will vary depending on the deformation mode, such as convex upward and downward, due to heat dissipation under field conditions. In addition, a reliability prediction method for thermal fatigue failure of solder bumps based on coupled thermal-stress analysis and statistical and probabilistic methods was proposed in order to select a suitable packaging solution at an early stage of design. It was found that the sensitivity of uncertain variables and the thermal fatigue life distribution of solder joints could change significantly depending on a combination of factors concerning the failure sites of solder bumps and the boundary conditions of the motherboard.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"81 1","pages":"347-358"},"PeriodicalIF":0.0,"publicationDate":"2010-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1115/IMECE2006-13800","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"63514408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Harmonic and Random Vibration Durability of SAC305 and Sn37Pb Solder Alloys","authors":"Y. Zhou, M. Al-Bassyiouni, A. Dasgupta","doi":"10.1109/TCAPT.2009.2036834","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2036834","url":null,"abstract":"In this paper, durability tests were conducted on both SAC305 and Sn37Pb solder interconnects using both harmonic and random vibration. The test specimens consist of daisy-chained printed wiring boards (PWBs) with several different surface-mount component styles. Modal testing was first conducted on a test PWB to determine the natural frequencies and mode shapes. The PWB was then subjected to narrow-band excitation at its first natural frequency. Electrical continuity of the daisy-chain nets was monitored to measure the time-to-failure (and hence cycles-to-failure) of the interconnects. The response history of the PWB was recorded with strain gages located near the components of interest. Finite element analysis (FEA) was conducted for each component type, to estimate the transfer function between the flexural strain of the PWB and the strain in the critical solder joint. The predicted strain transfer function was then combined with the measured PWB strain response history to estimate the strain history in the critical solder joints. The solder strain history was used, in conjunction with the failure history, to estimate lower bounds for the fatigue durability (S-N curves) of the solder interconnects. In the first part of this paper, the results show that the SAC305 interconnects are marginally less durable than Sn37Pb interconnects for the harmonic excitation range used in this paper. The durability model constants are found to be very sensitive to the solder stress-strain curve assumed in the FEA. Since the stress-strain properties reported in the literature for these solder alloys vary significantly, the solder stress-strain curves were parametrically varied in the FEA, to assess the resulting effect on the estimated S-N curves. In the second part of this paper, random-vibration tests were conducted to assess durability under step-stress, broad-band excitation. Conventional cycle counting techniques were used to quantify the random excitation histories in terms of range distribution functions. Using the same time-domain vibration fatigue analysis used earlier for narrow-band excitation, the durability trend for the corresponding SAC305 and Sn37Pb solder interconnects under broad-band excitation was found to be similar to that found earlier under harmonic vibration excitation. Comparison between the durability prediction and test results provides a good understanding of the effect of stress-strain behavior on the fatigue constants of these solder materials. The best set of material properties was then used to verify the durability of leadless chip resistor interconnects under quasi-static mechanical cycling.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"319-328"},"PeriodicalIF":0.0,"publicationDate":"2010-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2036834","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}