Journal of Systems Architecture最新文献

{"title":"A transformation strategy for process partitioning in hierarchical concurrent process networks","authors":"Fahimeh Bahrami,&nbsp;Ingo Sander","doi":"10.1016/j.sysarc.2025.103509","DOIUrl":"10.1016/j.sysarc.2025.103509","url":null,"abstract":"<div><div>Concurrent process networks are a widely used parallel programming model for designing multiprocessor embedded systems, where system functionality is decomposed into processes that communicate via signals. These processes can be mapped onto different processing elements and executed concurrently. While the initial process network is designed to effectively capture high-level parallelism, it may not fully exploit the available parallelism. To enhance concurrency and balance workload distribution, process partitioning transformations are applied, restructuring process networks to expose finer-grained parallelism. The effectiveness of these transformations, however, depends on how well they align with the underlying hardware’s parallel capabilities.</div><div>A variety of partitioning transformations have been introduced for process networks constructed using <em>higher-order functions</em> in the form of <em>process constructors</em> and <em>data-parallel skeletons</em>. For such networks, algebraic laws of functions provide a principled foundation for defining transformation rules, enabling a systematic and non-ad-hoc approach to process network modification. However, selecting the most suitable transformation to optimize key performance metrics remains an open challenge. To address this, we propose a <em>transformation strategy</em> that systematically identifies the most effective partitioning transformations. Our approach introduces evaluation metrics and analytical models to assess the impact of parametric transformations across different configurations. We validate the proposed strategy through the transformation of two image processing algorithms, demonstrating that our analytical models correctly predict the most suitable transformations for enhancing parallelism and performance.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103509"},"PeriodicalIF":3.7,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144596256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DLLPM: Dual-layer location privacy matching in V2V energy trading","authors":"Saad Masood ,&nbsp;Muneeb Ul Hassan ,&nbsp;Pei-Wei Tsai ,&nbsp;Jinjun Chen","doi":"10.1016/j.sysarc.2025.103507","DOIUrl":"10.1016/j.sysarc.2025.103507","url":null,"abstract":"<div><div>The recent increase in Electric Vehicles (EVs) on the road has highlighted privacy concerns, particularly in the Vehicle-to-Vehicle (V2V) energy trading scenario. Ensuring location privacy in Vehicular Ad Hoc Networks (VANETs) is crucial for user confidentiality. Existing privacy techniques in the V2V paradigm protect the location coordinates of the EVs, but privacy risks persist after EVs are matched. In this paper, we introduce a dual-layer location privacy matching (DLLPM) technique to enhance the privacy of V2V matching. Our approach utilizes Laplace differential privacy and partial homomorphic encryption, ensuring that the EV’s private data remains inaccessible to both participants and adversaries. We introduce a noise addition and clipping algorithm to obfuscate EV coordinates within a defined radius. Encrypted distance-based preference lists are generated using partial homomorphic encryption to establish differentially private stable matches. DLLPM ensures EV location privacy throughout the matching process and mitigates the risk of location privacy leakage even after suppliers and demanders exchange location information. Theoretical analysis and experimental results confirm the efficiency of DLLPM, demonstrating robust privacy preservation with a computational complexity of <span><math><mrow><mi>O</mi><mrow><mo>(</mo><msup><mrow><mi>n</mi></mrow><mrow><mn>2</mn></mrow></msup><mo>log</mo><mi>n</mi><mi>⋅</mi><mrow><mo>(</mo><msub><mrow><mi>C</mi></mrow><mrow><mtext>enc</mtext></mrow></msub><mo>+</mo><msub><mrow><mi>C</mi></mrow><mrow><mtext>addHE</mtext></mrow></msub><mo>+</mo><msub><mrow><mi>C</mi></mrow><mrow><mtext>subHE</mtext></mrow></msub><mo>+</mo><msub><mrow><mi>C</mi></mrow><mrow><mtext>dec</mtext></mrow></msub><mo>)</mo></mrow><mo>)</mo></mrow></mrow></math></span>. We further evaluate computational performance using 128-bit and 256-bit encryption, showing that DLLPM achieves private and efficient matching in the V2V trading paradigm.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103507"},"PeriodicalIF":3.7,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144588014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Data-driven power modeling and monitoring via hardware performance counter tracking","authors":"Sergio Mazzola ,&nbsp;Gabriele Ara ,&nbsp;Thomas Benz ,&nbsp;Björn Forsberg ,&nbsp;Tommaso Cucinotta ,&nbsp;Luca Benini","doi":"10.1016/j.sysarc.2025.103504","DOIUrl":"10.1016/j.sysarc.2025.103504","url":null,"abstract":"<div><div>Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an affordable power budget, often under real-time constraints. Hardware heterogeneity and parallelism help address the efficiency challenge, but greatly complicate online power consumption assessments, which are essential for dynamic hardware and software stack adaptations. We introduce a novel power modeling methodology with state-of-the-art accuracy, low overhead, and high responsiveness, whose implementation does not rely on microarchitectural details. Our methodology identifies the Performance Monitoring Counters (PMCs) with the highest linear correlation to the power consumption of each hardware sub-system, for each Dynamic Voltage and Frequency Scaling (DVFS) state. The individual, simple models are composed into a complete model that effectively describes the power consumption of the whole system, achieving high accuracy and low overhead. Our evaluation reports an average estimation error of 7.5% for power consumption and 1.3% for energy. We integrate these models in the Linux kernel with Runmeter, an open-source, PMC-based monitoring framework. Runmeter manages PMC sampling and processing, enabling the execution of our power models at runtime. With a worst-case time overhead of only 0.7%, Runmeter provides responsive and accurate power measurements directly in the kernel. This information can be employed for actuation policies in workload-aware DVFS and power-aware, closed-loop task scheduling.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103504"},"PeriodicalIF":3.7,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144513954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature and deadline aware runtime resource management with workload prediction for heterogeneous multi-core platforms","authors":"Mina Niknafs,&nbsp;Petru Eles,&nbsp;Zebo Peng","doi":"10.1016/j.sysarc.2025.103506","DOIUrl":"10.1016/j.sysarc.2025.103506","url":null,"abstract":"<div><div>Contemporary embedded platforms necessitate advanced resource management techniques to effectively utilize their diverse computational resources. Usually these platforms encounter fluctuations in workloads, making workload prediction have the potential to enhance resource management efficiency. In addition, in modern multi-core systems, there is a discernible tendency for processing cores to decrease in size relative to power consumption. This reduction in core size contributes to higher power density within the chips, leading to elevated chip temperatures. Therefore, addressing the temperature issue becomes critical. This paper introduces a prediction-based and temperature-aware resource management heuristic designed to meet task deadlines, while simultaneously considering energy minimization. When evaluated on real-life workload traces, the proposed method achieves a 5.5% increase in acceptance rate with one-step-ahead prediction and an 8.9% increase with four-steps-ahead prediction in a temperature-aware context, compared to scenarios without prediction.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103506"},"PeriodicalIF":3.7,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144523542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient one-to-one sharing: Public key matchmaking encryption","authors":"Yunhao Ling ,&nbsp;Guang Zhang ,&nbsp;Jie Chen ,&nbsp;Haifeng Qian","doi":"10.1016/j.sysarc.2025.103492","DOIUrl":"10.1016/j.sysarc.2025.103492","url":null,"abstract":"<div><div>Identity-Based Matchmaking Encryption (IB-ME) enables both the sender and the receiver to respectively specify an identity that the other party must satisfy, in order to reveal the messages. IB-ME is actually a one-to-one matchmaking encryption, and has many applications such as secure data sharing and non-interactive secret handshake protocol. However, the system requires a central authority to generate encryption keys and decryption keys for all users, which could lead to key escrow problem, single-point failure and performance bottleneck. The goal of this paper is to remove any authority from the system. We propose a matchmaking encryption in public-key setting, named Public Key Matchmaking Encryption (PK-ME). We give the formal syntax and security definition of PK-ME, present a lightweight PK-ME scheme, and formally prove its security in the random model. Finally, we conduct experiments to show the practicability of the scheme. In particular, compared to the related ME schemes, our encryption and decryption are very efficient, and our PK-ME scheme has shorter parameters.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103492"},"PeriodicalIF":3.7,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144502063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A survey on versatile embedded Machine Learning hardware acceleration","authors":"Pierre Garreau ,&nbsp;Pascal Cotret ,&nbsp;Julien Francq ,&nbsp;Jean-Christophe Cexus ,&nbsp;Loïc Lagadec","doi":"10.1016/j.sysarc.2025.103501","DOIUrl":"10.1016/j.sysarc.2025.103501","url":null,"abstract":"<div><div>This survey investigates recent developments in versatile embedded Machine Learning (ML) hardware acceleration. Various architectural approaches for efficient implementation of ML algorithms on resource-constrained devices are analyzed, focusing on three key aspects: performance optimization, embedded system considerations (throughput, latency, energy efficiency) and multi-application support. Nevertheless, it does not take into account attacks and defenses of ML architectures themselves. The survey then explores different hardware acceleration strategies, from custom RISC-V instructions to specialized Processing Elements (PEs), Processing-in-Memory (PiM) architectures and co-design approaches. Notable innovations include flexible bit-precision support, reconfigurable PEs, and optimal memory management techniques for reducing weights and (hyper)-parameters movements overhead. Subsequently, these architectures are evaluated based on the aforementioned key aspects. Our analysis shows that relevant and robust embedded ML acceleration requires careful consideration of the trade-offs between computational capability, power consumption, and architecture flexibility, depending on the application.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103501"},"PeriodicalIF":3.7,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144470141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inference framework supporting parallel execution across heterogeneous accelerators","authors":"Philkyue Shin ,&nbsp;Myungsun Kim ,&nbsp;Seongsoo Hong","doi":"10.1016/j.sysarc.2025.103508","DOIUrl":"10.1016/j.sysarc.2025.103508","url":null,"abstract":"<div><div>The growing demand for on-device deep learning inference, particularly in latency-sensitive applications, has driven the adoption of heterogeneous accelerators that incorporate GPUs, DSPs, and NPUs. While these accelerators offer improved energy efficiency, their heterogeneity introduces significant programming complexity due to reliance on vendor-specific APIs. Existing deep learning inference frameworks, such as LiteRT, provide high-level APIs and support multiple backend APIs. However, they lack the ability to exploit parallel execution across heterogeneous accelerators. This paper introduces a novel inference framework that overcomes this limitation. Our framework utilizes a batch inference API to enable parallel execution across heterogeneous accelerators. The framework schedules heterogeneous accelerators to process batched inputs concurrently. To address the challenge of integrating commercial NPU APIs that do not support LiteRT, we develop a portable hooking engine. Furthermore, the framework mitigates accuracy inconsistencies arising from diverse quantization methods by dynamically adjusting postprocessing parameters to balance accuracy and latency. The proposed framework minimizes both average turnaround time and postprocessing time. Experimental results on a Qualcomm SA8195 SoC with Mobilint and Hailo NPUs demonstrate significant performance improvements compared to existing inference frameworks.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103508"},"PeriodicalIF":3.7,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144513953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache","authors":"Xiangrong Xu ,&nbsp;Liang Wang ,&nbsp;Limin Xiao ,&nbsp;Lei Liu ,&nbsp;Zihao Zhou ,&nbsp;Yuanqiu Lv ,&nbsp;Li Ruan ,&nbsp;Xilong Xie ,&nbsp;Meng Han ,&nbsp;Xiaojian Liao","doi":"10.1016/j.sysarc.2025.103500","DOIUrl":"10.1016/j.sysarc.2025.103500","url":null,"abstract":"<div><div>Remote memory accesses in multi-chip GPUs pose a major performance bottleneck due to high latency and inter-chip bandwidth contention. Exploiting intra-chip locality alleviates this bottleneck by serving memory accesses locally and reducing cross-chip traffic. Yet, conventional coarse-grained approaches to exploiting locality in multi-chip GPUs often incur excessive overhead, limiting their potential performance benefits. To this end, we propose TLS-Cache, a two-level shared L1 cache that efficiently exploits intra-chip locality without additional cache capacity. It mitigates high-latency remote memory accesses by enabling fine-grained data reuse through cluster-shared and remote-shared L1 caches, which capture locality within and across streaming multiprocessor clusters, respectively. These two caches work cooperatively to maximize the exploitation of intra-chip locality and deliver measurable performance gains. Experimental results show that TLS-Cache improves instructions per cycle by 30.2% on average, compared with the baseline 4-chip GPU with private L1 caches.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103500"},"PeriodicalIF":3.7,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ZoomDB: Building cost-effective key–value store engine on ZNS SSD and SMR HDD","authors":"Shiqiang Nie ,&nbsp;Chi Zhang ,&nbsp;Menghan Li ,&nbsp;Fangxing Yu ,&nbsp;Yaming Li ,&nbsp;Weiguo Wu","doi":"10.1016/j.sysarc.2025.103465","DOIUrl":"10.1016/j.sysarc.2025.103465","url":null,"abstract":"<div><div>Log-Structured Merge tree (LSM-tree) based key–Value (KV) stores have become critical components in managing data for write-intensive cloud applications. With the explosive growth of unstructured data, emerging host-managed zoned storage solutions, such as high-performance Zoned NameSpace Solid State Drive (ZNS SSD) and large-capacity Shingled Magnetic Recording Hard Disk Drive (SMR HDD), present an ideal opportunity for efficient data storage. However, The state-of-the-art scheme partitions the LSM-tree on hybrid storage, placing lower levels on high-performance devices and higher levels on large-capacity devices, but it fails to address challenges in data layout and garbage collection on the hybrid storage system equipped with ZNS SSD and SMR HDD.</div><div>In this paper, we propose ZoomDB, an LSM-tree KV store engine designed around KV separation and tailored for hybrid zoned storage devices. First, we integrate KV separation with zone management in LSM-tree-based hybrid storage. Specifically, keys and low-level values are placed in high-performance zones on ZNS SSDs, while high-level values are stored in large-capacity zones on SMR HDDs, optimizing both performance and storage efficiency. To further enhance data management, we introduce a hotness identification mechanism that classifies values based on access frequency, storing hot and cold values in separate zones. Finally, we propose diversity GC tailored to zones with varying access frequencies, effectively reducing data migration overhead. We implement and evaluate ZoomDB on real ZNS SSD and SMR HDD. The evaluation results demonstrate that ZoomDB reduces the number of GC-triggered writes by 77.5% on average compared to WiscKey. It achieves throughput gains of 1.79<span><math><mo>×</mo></math></span> , 3.13<span><math><mo>×</mo></math></span> , 4.01<span><math><mo>×</mo></math></span> , 4.25<span><math><mo>×</mo></math></span> , and 4.32<span><math><mo>×</mo></math></span> over WiscKey+, WiscKey, GearDB, ZoneKV, and LevelDB, respectively.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103465"},"PeriodicalIF":3.7,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LB-CLBS: Lattice-based certificateless blind signature scheme for vehicle sensing within intelligent transportation","authors":"Sheng-wei Xu ,&nbsp;Shu-han Yu ,&nbsp;Wan-Lu Liu ,&nbsp;Zi-Yan Yue ,&nbsp;Yi-Long Liu","doi":"10.1016/j.sysarc.2025.103491","DOIUrl":"10.1016/j.sysarc.2025.103491","url":null,"abstract":"<div><div>In intelligent transportation, sensors installed on vehicles provide various intelligence services to relevant management departments by collecting road information and other sensing data. Government administrations use these data to provide convenient services to vehicle users and promote intelligent transportation development. However, as the importance of data continues to grow, the threats to the privacy of sensing data have increased dramatically. Malicious attackers can illegally obtain sensitive information about a vehicle, including speed, location, behavioral preferences and other data. Furthermore, the rise of quantum computing continues to pose a challenge to vehicle privacy data. Therefore, in this paper, we propose a new lattice-based certificateless blind signature (LB-CLBS) scheme using the module lattice to enhance vehicle privacy protection in intelligent transportation environments. Concretely, we use certificateless cryptography to construct a blind signature scheme based on the basic framework of Dilithium, which both ensures that the scheme is post-quantum and solves the key escrow problem in traditional cryptosystems. Based on the module version of Small Integer Solution (MSIS) and module version of Learning With Error (MLWE) hard problems, we prove that the LB-CLBS scheme is existential unforgeability under adaptively chosen message attacks (EUF-CMA) in the random oracle model. The performance evaluation shows that our scheme has an advantage over the previous scheme in every security performance. In addition, the computational efficiency of our scheme is improved by at least 70% compared with the previous schemes.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103491"},"PeriodicalIF":3.7,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}