Configuration-aware approaches for enhancing energy efficiency in FPGA-based deep learning accelerators

In the rapidly evolving domain of the Internet of Things (IoT), this study focuses on enhancing the energy efficiency of Deep Learning accelerators implemented on FPGA-based heterogeneous platforms aligned with the principles of sustainable computing. Diverging from the conventional focus on the inference phase, this research introduces innovative optimizations aimed at minimizing the overhead associated with the FPGA configuration phase. Our investigation achieved a remarkable 40.13-fold reduction in configuration energy each time the FPGA is powered on through precise fine-tuning of configuration parameters. Furthermore, the implementation of our Idle-Waiting strategy significantly reduced the overall energy consumption across requests. Under scenarios with regular request periods, the enhanced Idle-Waiting strategy augmented with power-saving methods, outperforms the traditional On-Off strategy in duty-cycle mode for request periods extending up to 499.06 ms. This enhancement is most pronounced at a 40 ms request period, where it increases the system’s operational lifetime by a factor of 12.39 within a 4147 J energy budget. Additionally, this paper introduces an adaptive strategy switching approach to manage scenarios with irregular request periods, employing both predefined and learnable threshold methods. This approach is not only more consistently stable than single-strategy methods but also generally outperforms them. Within this approach, our learnable threshold experiences only a 10% performance drop compared to the future-aware strategy and is at least 6% better than using single-strategy methods. These results underscore the significant potential for deploying more energy-efficient and sustainable systems within IoT applications. Future research will explore the application of these power-saving techniques to a broader spectrum of tasks on diverse FPGA platforms.