Journal of Systems Architecture最新文献

{"title":"Data-driven power modeling and monitoring via hardware performance counter tracking","authors":"Sergio Mazzola ,&nbsp;Gabriele Ara ,&nbsp;Thomas Benz ,&nbsp;Björn Forsberg ,&nbsp;Tommaso Cucinotta ,&nbsp;Luca Benini","doi":"10.1016/j.sysarc.2025.103504","DOIUrl":"10.1016/j.sysarc.2025.103504","url":null,"abstract":"<div><div>Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an affordable power budget, often under real-time constraints. Hardware heterogeneity and parallelism help address the efficiency challenge, but greatly complicate online power consumption assessments, which are essential for dynamic hardware and software stack adaptations. We introduce a novel power modeling methodology with state-of-the-art accuracy, low overhead, and high responsiveness, whose implementation does not rely on microarchitectural details. Our methodology identifies the Performance Monitoring Counters (PMCs) with the highest linear correlation to the power consumption of each hardware sub-system, for each Dynamic Voltage and Frequency Scaling (DVFS) state. The individual, simple models are composed into a complete model that effectively describes the power consumption of the whole system, achieving high accuracy and low overhead. Our evaluation reports an average estimation error of 7.5% for power consumption and 1.3% for energy. We integrate these models in the Linux kernel with Runmeter, an open-source, PMC-based monitoring framework. Runmeter manages PMC sampling and processing, enabling the execution of our power models at runtime. With a worst-case time overhead of only 0.7%, Runmeter provides responsive and accurate power measurements directly in the kernel. This information can be employed for actuation policies in workload-aware DVFS and power-aware, closed-loop task scheduling.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103504"},"PeriodicalIF":3.7,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144513954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient one-to-one sharing: Public key matchmaking encryption","authors":"Yunhao Ling ,&nbsp;Guang Zhang ,&nbsp;Jie Chen ,&nbsp;Haifeng Qian","doi":"10.1016/j.sysarc.2025.103492","DOIUrl":"10.1016/j.sysarc.2025.103492","url":null,"abstract":"<div><div>Identity-Based Matchmaking Encryption (IB-ME) enables both the sender and the receiver to respectively specify an identity that the other party must satisfy, in order to reveal the messages. IB-ME is actually a one-to-one matchmaking encryption, and has many applications such as secure data sharing and non-interactive secret handshake protocol. However, the system requires a central authority to generate encryption keys and decryption keys for all users, which could lead to key escrow problem, single-point failure and performance bottleneck. The goal of this paper is to remove any authority from the system. We propose a matchmaking encryption in public-key setting, named Public Key Matchmaking Encryption (PK-ME). We give the formal syntax and security definition of PK-ME, present a lightweight PK-ME scheme, and formally prove its security in the random model. Finally, we conduct experiments to show the practicability of the scheme. In particular, compared to the related ME schemes, our encryption and decryption are very efficient, and our PK-ME scheme has shorter parameters.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103492"},"PeriodicalIF":3.7,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144502063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A survey on versatile embedded Machine Learning hardware acceleration","authors":"Pierre Garreau ,&nbsp;Pascal Cotret ,&nbsp;Julien Francq ,&nbsp;Jean-Christophe Cexus ,&nbsp;Loïc Lagadec","doi":"10.1016/j.sysarc.2025.103501","DOIUrl":"10.1016/j.sysarc.2025.103501","url":null,"abstract":"<div><div>This survey investigates recent developments in versatile embedded Machine Learning (ML) hardware acceleration. Various architectural approaches for efficient implementation of ML algorithms on resource-constrained devices are analyzed, focusing on three key aspects: performance optimization, embedded system considerations (throughput, latency, energy efficiency) and multi-application support. Nevertheless, it does not take into account attacks and defenses of ML architectures themselves. The survey then explores different hardware acceleration strategies, from custom RISC-V instructions to specialized Processing Elements (PEs), Processing-in-Memory (PiM) architectures and co-design approaches. Notable innovations include flexible bit-precision support, reconfigurable PEs, and optimal memory management techniques for reducing weights and (hyper)-parameters movements overhead. Subsequently, these architectures are evaluated based on the aforementioned key aspects. Our analysis shows that relevant and robust embedded ML acceleration requires careful consideration of the trade-offs between computational capability, power consumption, and architecture flexibility, depending on the application.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103501"},"PeriodicalIF":3.7,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144470141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inference framework supporting parallel execution across heterogeneous accelerators","authors":"Philkyue Shin ,&nbsp;Myungsun Kim ,&nbsp;Seongsoo Hong","doi":"10.1016/j.sysarc.2025.103508","DOIUrl":"10.1016/j.sysarc.2025.103508","url":null,"abstract":"<div><div>The growing demand for on-device deep learning inference, particularly in latency-sensitive applications, has driven the adoption of heterogeneous accelerators that incorporate GPUs, DSPs, and NPUs. While these accelerators offer improved energy efficiency, their heterogeneity introduces significant programming complexity due to reliance on vendor-specific APIs. Existing deep learning inference frameworks, such as LiteRT, provide high-level APIs and support multiple backend APIs. However, they lack the ability to exploit parallel execution across heterogeneous accelerators. This paper introduces a novel inference framework that overcomes this limitation. Our framework utilizes a batch inference API to enable parallel execution across heterogeneous accelerators. The framework schedules heterogeneous accelerators to process batched inputs concurrently. To address the challenge of integrating commercial NPU APIs that do not support LiteRT, we develop a portable hooking engine. Furthermore, the framework mitigates accuracy inconsistencies arising from diverse quantization methods by dynamically adjusting postprocessing parameters to balance accuracy and latency. The proposed framework minimizes both average turnaround time and postprocessing time. Experimental results on a Qualcomm SA8195 SoC with Mobilint and Hailo NPUs demonstrate significant performance improvements compared to existing inference frameworks.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103508"},"PeriodicalIF":3.7,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144513953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache","authors":"Xiangrong Xu ,&nbsp;Liang Wang ,&nbsp;Limin Xiao ,&nbsp;Lei Liu ,&nbsp;Zihao Zhou ,&nbsp;Yuanqiu Lv ,&nbsp;Li Ruan ,&nbsp;Xilong Xie ,&nbsp;Meng Han ,&nbsp;Xiaojian Liao","doi":"10.1016/j.sysarc.2025.103500","DOIUrl":"10.1016/j.sysarc.2025.103500","url":null,"abstract":"<div><div>Remote memory accesses in multi-chip GPUs pose a major performance bottleneck due to high latency and inter-chip bandwidth contention. Exploiting intra-chip locality alleviates this bottleneck by serving memory accesses locally and reducing cross-chip traffic. Yet, conventional coarse-grained approaches to exploiting locality in multi-chip GPUs often incur excessive overhead, limiting their potential performance benefits. To this end, we propose TLS-Cache, a two-level shared L1 cache that efficiently exploits intra-chip locality without additional cache capacity. It mitigates high-latency remote memory accesses by enabling fine-grained data reuse through cluster-shared and remote-shared L1 caches, which capture locality within and across streaming multiprocessor clusters, respectively. These two caches work cooperatively to maximize the exploitation of intra-chip locality and deliver measurable performance gains. Experimental results show that TLS-Cache improves instructions per cycle by 30.2% on average, compared with the baseline 4-chip GPU with private L1 caches.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103500"},"PeriodicalIF":3.7,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ZoomDB: Building cost-effective key–value store engine on ZNS SSD and SMR HDD","authors":"Shiqiang Nie ,&nbsp;Chi Zhang ,&nbsp;Menghan Li ,&nbsp;Fangxing Yu ,&nbsp;Yaming Li ,&nbsp;Weiguo Wu","doi":"10.1016/j.sysarc.2025.103465","DOIUrl":"10.1016/j.sysarc.2025.103465","url":null,"abstract":"<div><div>Log-Structured Merge tree (LSM-tree) based key–Value (KV) stores have become critical components in managing data for write-intensive cloud applications. With the explosive growth of unstructured data, emerging host-managed zoned storage solutions, such as high-performance Zoned NameSpace Solid State Drive (ZNS SSD) and large-capacity Shingled Magnetic Recording Hard Disk Drive (SMR HDD), present an ideal opportunity for efficient data storage. However, The state-of-the-art scheme partitions the LSM-tree on hybrid storage, placing lower levels on high-performance devices and higher levels on large-capacity devices, but it fails to address challenges in data layout and garbage collection on the hybrid storage system equipped with ZNS SSD and SMR HDD.</div><div>In this paper, we propose ZoomDB, an LSM-tree KV store engine designed around KV separation and tailored for hybrid zoned storage devices. First, we integrate KV separation with zone management in LSM-tree-based hybrid storage. Specifically, keys and low-level values are placed in high-performance zones on ZNS SSDs, while high-level values are stored in large-capacity zones on SMR HDDs, optimizing both performance and storage efficiency. To further enhance data management, we introduce a hotness identification mechanism that classifies values based on access frequency, storing hot and cold values in separate zones. Finally, we propose diversity GC tailored to zones with varying access frequencies, effectively reducing data migration overhead. We implement and evaluate ZoomDB on real ZNS SSD and SMR HDD. The evaluation results demonstrate that ZoomDB reduces the number of GC-triggered writes by 77.5% on average compared to WiscKey. It achieves throughput gains of 1.79<span><math><mo>×</mo></math></span> , 3.13<span><math><mo>×</mo></math></span> , 4.01<span><math><mo>×</mo></math></span> , 4.25<span><math><mo>×</mo></math></span> , and 4.32<span><math><mo>×</mo></math></span> over WiscKey+, WiscKey, GearDB, ZoneKV, and LevelDB, respectively.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103465"},"PeriodicalIF":3.7,"publicationDate":"2025-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"LB-CLBS: Lattice-based certificateless blind signature scheme for vehicle sensing within intelligent transportation","authors":"Sheng-wei Xu ,&nbsp;Shu-han Yu ,&nbsp;Wan-Lu Liu ,&nbsp;Zi-Yan Yue ,&nbsp;Yi-Long Liu","doi":"10.1016/j.sysarc.2025.103491","DOIUrl":"10.1016/j.sysarc.2025.103491","url":null,"abstract":"<div><div>In intelligent transportation, sensors installed on vehicles provide various intelligence services to relevant management departments by collecting road information and other sensing data. Government administrations use these data to provide convenient services to vehicle users and promote intelligent transportation development. However, as the importance of data continues to grow, the threats to the privacy of sensing data have increased dramatically. Malicious attackers can illegally obtain sensitive information about a vehicle, including speed, location, behavioral preferences and other data. Furthermore, the rise of quantum computing continues to pose a challenge to vehicle privacy data. Therefore, in this paper, we propose a new lattice-based certificateless blind signature (LB-CLBS) scheme using the module lattice to enhance vehicle privacy protection in intelligent transportation environments. Concretely, we use certificateless cryptography to construct a blind signature scheme based on the basic framework of Dilithium, which both ensures that the scheme is post-quantum and solves the key escrow problem in traditional cryptosystems. Based on the module version of Small Integer Solution (MSIS) and module version of Learning With Error (MLWE) hard problems, we prove that the LB-CLBS scheme is existential unforgeability under adaptively chosen message attacks (EUF-CMA) in the random oracle model. The performance evaluation shows that our scheme has an advantage over the previous scheme in every security performance. In addition, the computational efficiency of our scheme is improved by at least 70% compared with the previous schemes.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103491"},"PeriodicalIF":3.7,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SECP-AKE: Secure and efficient certificateless-password-based authenticated key exchange protocol for smart healthcare systems","authors":"Zhiqiang Zhao ,&nbsp;Xuexian Hu ,&nbsp;Yining Liu ,&nbsp;Jianghong Wei ,&nbsp;Yuanjun Xia ,&nbsp;Yangfan Liang","doi":"10.1016/j.sysarc.2025.103485","DOIUrl":"10.1016/j.sysarc.2025.103485","url":null,"abstract":"<div><div>Due to the importance and sensitivity of medical data, the security protection and privacy preservation of the Healthcare Internet of Things (IoT) are current research hotspots. However, existing research schemes still suffer from incomplete security properties, imperfect authentication mechanisms, and inadequate privacy preservation. Therefore, this paper presents SECP-AKE, a secure and efficient certificateless-password-based authenticated key exchange protocol for IoT-based smart healthcare, which enables batch authentication, resists physical attacks, and provides strong anonymity. Specifically, using certificateless cryptography, the SECP-AKE protocol enables batch authentication of authorized users and devices while also resolving the key escrow problem. In particular, the SECP-AKE protocol incorporates Physical Unclonable Functions (PUFs) to resist physical attacks, thus enhancing device security and ensuring reliable medical service delivery. Additionally, the design of a pseudonym update mechanism can achieve user unlinkability, thereby providing enhanced privacy preservation. The results from both formal verification using SVO logic and informal security analyses demonstrate that the SECP-AKE protocol is secure and offers more comprehensive security properties. Meanwhile, the use of a well-known automated security verification tool Scyther further evaluates the protocol’s security reliability. Ultimately, comparative experiments on communication overhead and computational overhead demonstrate that the SECP-AKE protocol is efficient and feasible compared to state-of-the-art existing works.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103485"},"PeriodicalIF":3.7,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144335670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Is it worth the energy? An in-depth study on the energy efficiency of data augmentation strategies for finetuning-based low/few-shot object detection","authors":"Vladislav Li ,&nbsp;Georgios Tsoumplekas ,&nbsp;Ilias Siniosoglou ,&nbsp;Panagiotis Sarigiannidis ,&nbsp;Vasileios Argyriou","doi":"10.1016/j.sysarc.2025.103484","DOIUrl":"10.1016/j.sysarc.2025.103484","url":null,"abstract":"<div><div>Current methods for low- and few-shot object detection have primarily focused on enhancing model performance for detecting objects. One common approach to achieve this is by combining model finetuning with data augmentation strategies. However, little attention has been given to the energy efficiency of these approaches in data-scarce regimes. This paper seeks to conduct a comprehensive empirical study that examines both model performance and energy efficiency of custom data augmentations and automated data augmentation selection strategies when combined with a lightweight object detector. The methods are evaluated in four different benchmark datasets in terms of their performance and energy consumption, providing valuable insights regarding reaching an optimal tradeoff between these two objectives. Additionally, to better quantify this tradeoff, we propose a novel metric named modified Efficiency Factor that combines both of these conflicting objectives in a single metric and thus enables gaining insights into the effectiveness of the examined models and data augmentation strategies when considering both performance and efficiency. Consequently, it is shown that while some broader guidelines regarding appropriate data augmentation selections can be provided based on the obtained performance and energy efficiency results, in many cases, the performance gains of data augmentation strategies are overshadowed by their increased energy usage, necessitating the development of more energy-efficient data augmentation strategies to address data scarcity.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103484"},"PeriodicalIF":3.7,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lightweight and anonymous certificateless signcryption scheme for multi-receiver","authors":"Qingqing Xie,&nbsp;Liangqing Song","doi":"10.1016/j.sysarc.2025.103482","DOIUrl":"10.1016/j.sysarc.2025.103482","url":null,"abstract":"<div><div>This paper proposes an innovative certificateless signcryption scheme, which achieves lightweight computation and anonymity for both the sender and the receiver. By replacing the bilinear operation with elliptic curve scalar multiplication, the proposed scheme significantly reduces computational overhead, making it suitable for resource-limited devices. Furthermore, the scheme achieves the anonymity of both sender and receiver, by embedding the sender’s real identity within the set of disguises and concealing the receiver’s identity through pseudonyms. It also supports multiple receivers. It achieves a signcryption time of 1.134 ms, an unsigncryption time of 0.542 ms, and a ciphertext size of 280 bytes. Compared with some existing schemes that achieve sender or receiver anonymity and involve no pairing operations, the cost of signcryption and unsigncryption is reduced by 50% and 86% at most respectively. Through a formal security proof, we demonstrate that the proposed scheme ensures confidentiality and unforgeability.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"167 ","pages":"Article 103482"},"PeriodicalIF":3.7,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}