Journal of Systems Architecture最新文献

Electric vehicle charging network security: A survey

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2025.103337

Xin Hu , XiaoNing Jiang , Jie Zhang , ShouGuang Wang , MengChu Zhou , Bei Zhang , ZhiGang Gan , BinXiao Yu

{"title":"Electric vehicle charging network security: A survey","authors":"Xin Hu , XiaoNing Jiang , Jie Zhang , ShouGuang Wang , MengChu Zhou , Bei Zhang , ZhiGang Gan , BinXiao Yu","doi":"10.1016/j.sysarc.2025.103337","DOIUrl":"10.1016/j.sysarc.2025.103337","url":null,"abstract":"<div><div>With the rising number of electric vehicles, their charging network has expanded into a vast and intricate system involving multiple stakeholders and numerous charging service entities. It relies on various technologies, such as communication protocols, network connections, and data transmission, leading to the generation of substantial amounts of sensitive data. Ensuring its high security requires the implementation of a comprehensive array of security measures, including stringent identity authentication and access control techniques, cryptographic solutions to safeguard data, and diverse strategies for detecting and countering network attacks. In this article, we present a comprehensive overview of the mainstream architectures and communication protocols in electric vehicle charging networks. We also provide a brief introduction to other protocols used in charging networks and explore the charging infrastructure and its associated security requirements. We examine a charging network’s security challenges at its perception, network, and application layers, and summarize the important solutions proposed in recent literature. Additionally, we delve into privacy security and payment security in the charging business. We investigate the utilization of blockchain technology to safeguard charging networks. Finally, we highlight public safety issues of a charging network and suggest future research directions to steer further studies of charging network security.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"159 ","pages":"Article 103337"},"PeriodicalIF":3.7,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143133624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Distrusting cores by separating computation from isolation

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2024.103328

Nils Asmussen, Till Miemietz, Sebastian Haas, Michael Roitzsch

引用次数: 0

LicenseNet: Proactively safeguarding intellectual property of AI models through model license

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2025.103330

Peihao Li , Jie Huang , Shuaishuai Zhang

{"title":"LicenseNet: Proactively safeguarding intellectual property of AI models through model license","authors":"Peihao Li , Jie Huang , Shuaishuai Zhang","doi":"10.1016/j.sysarc.2025.103330","DOIUrl":"10.1016/j.sysarc.2025.103330","url":null,"abstract":"<div><div>With the widespread adoption of AI models in edge computing systems, these high-value models face significant risks of theft, misuse, and tampering due to the lower security and reliability of edge devices compared to the cloud. The leakage of models can result in substantial financial losses and security threats, making the protection of intellectual property (IP) crucial. Existing watermark-based IP verification techniques fail to proactively prevent infringement, while other active IP protection solutions often suffer from high overhead, low performance, and inadequate security. This paper proposes LicenseNet, an AI model IP protection framework based on licenses, which enables authorized access to models by embedding license features within them. We design a gradient optimization-based method for synchronizing license training with model parameters and introduce a random perturbation-based data standardization technique. This allows the trained model to generate correct inferences for license data while producing confusing results for original data, thus enhancing the security of the model on edge devices. Additionally, to enhance the model’s resistance against fine-tuning attacks, a supervised discrimination mechanism is incorporated. Experimental results demonstrate that LicenseNet achieves higher security, reduced performance loss, and an improvement in resistance to fine-tuning attacks by at least 29.03% compared to existing methods in edge computing environments.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"159 ","pages":"Article 103330"},"PeriodicalIF":3.7,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143133685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DBDAA: Dual blockchain and decentralized identifiers assisted anonymous authentication for building IoT

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2025.103334

Xiaohua Wu , Zheng Luo , Jun Cheng , Puyan Wang

{"title":"DBDAA: Dual blockchain and decentralized identifiers assisted anonymous authentication for building IoT","authors":"Xiaohua Wu , Zheng Luo , Jun Cheng , Puyan Wang","doi":"10.1016/j.sysarc.2025.103334","DOIUrl":"10.1016/j.sysarc.2025.103334","url":null,"abstract":"<div><div>The rapid advancements in the Internet of Things (IoT) and blockchain have made building IoT a critical element in modern intelligent building management. However, with the increasing adaptability of building IoT systems, concerns about data security and privacy have risen. Traditional solutions often rely on a single user identity, which poses security risks. Additionally, these solutions overlook the security of user permission information in access control systems. As a result, users with elevated permissions become prime targets for attacks. Existing key management mechanisms also have shortcomings, especially in key recovery processes. To address these issues, this paper proposes an identity authentication mechanism leveraging dual-blockchain and decentralized identifier (DID) technology. In the proposed mechanism, we develop a lightweight authentication scheme for devices. We also create a multi-DID model for users and further propose an anonymous authentication scheme, to safeguard data privacy, identity, and permission information, striking a balance between anonymity and oversight. Moreover, we design a key backup and recovery scheme to safeguard against key loss or damage, increasing system reliability. Experimental results demonstrate that our scheme enhances security while reducing computational and communication overhead.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"159 ","pages":"Article 103334"},"PeriodicalIF":3.7,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143133681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accelerating tensor multiplication by exploring hybrid product with hardware and software co-design

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2025.103333

Zhiyuan Zhang, Zhihua Fan, Wenming Li, Yuhang Qiu, Zhen Wang, Xiaochun Ye, Dongrui Fan, Xuejun An

{"title":"Accelerating tensor multiplication by exploring hybrid product with hardware and software co-design","authors":"Zhiyuan Zhang, Zhihua Fan, Wenming Li, Yuhang Qiu, Zhen Wang, Xiaochun Ye, Dongrui Fan, Xuejun An","doi":"10.1016/j.sysarc.2025.103333","DOIUrl":"10.1016/j.sysarc.2025.103333","url":null,"abstract":"<div><div>Tensor multiplication holds a pivotal position in numerous applications. The existing accelerators predominantly rely on inner or outer products for their computational strategies, yet these methodologies encounter obstacles such as excessive storage overhead, underutilization of parallelism, and merging costs. To tackle the challenges, we propose an acceleration technique that integrates a hybrid product approach with a tailored hardware. Our design can accommodate tensor multiplications of various scales, boasting exceptional scalability. First, we employ a hybrid product approach for tensor multiplications, strategically leveraging various methods – including inner, outer, and Hadamard products – to optimize different stages of submatrices computations. Second, we devise a dedicated architecture that seamlessly aligns with hybrid product, leveraging dataflow paradigm to map tensor multiplication efficiently onto the hardware. Third, we design a sliding-window partial reuse FIFO (SWFIFO), alongside a data reorder and scheduling unit to accelerate data retrieval. For general matrix multiplication (GEMM), our design demonstrates an average speedup of <span><math><mrow><mn>17</mn><mo>.</mo><mn>62</mn><mo>×</mo></mrow></math></span> and 9.47% energy consumption over Nvidia’s V100 GPU. Furthermore, it surpasses Google’s TPU (size of 256 × 256) by an average of <span><math><mrow><mn>3</mn><mo>.</mo><mn>76</mn><mo>×</mo></mrow></math></span>, TPUv2 (size of 128 × 128) by <span><math><mrow><mn>3</mn><mo>.</mo><mn>19</mn><mo>×</mo></mrow></math></span> and Eyeriss by <span><math><mrow><mn>3</mn><mo>.</mo><mn>8</mn><mo>×</mo></mrow></math></span>. When evaluated on eight neural network models, our design yields a performance boost of <span><math><mrow><mn>2</mn><mo>.</mo><mn>89</mn><mo>×</mo></mrow></math></span> over TPU and <span><math><mrow><mn>2</mn><mo>.</mo><mn>19</mn><mo>×</mo></mrow></math></span> over Eyeriss.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"159 ","pages":"Article 103333"},"PeriodicalIF":3.7,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143133682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Adapter-guided knowledge transfer for heterogeneous federated learning

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2025.103338

Shichong Liu , Haozhe Jin , Zhiwei Tang , Rui Zhai , Ke Lu , Junyang Yu , Chenxi Bai

引用次数: 0

Semi-clairvoyant scheduling in non-preemptive fixed-priority mixed-criticality systems

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2025.103332

Yi-Wen Zhang, Chen Ouyang

引用次数: 0

An energy-efficient near-data processing accelerator for DNNs to optimize memory accesses

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2024.103320

Bahareh Khabbazan, Mohammad Sabri, Marc Riera, Antonio González

{"title":"An energy-efficient near-data processing accelerator for DNNs to optimize memory accesses","authors":"Bahareh Khabbazan, Mohammad Sabri, Marc Riera, Antonio González","doi":"10.1016/j.sysarc.2024.103320","DOIUrl":"10.1016/j.sysarc.2024.103320","url":null,"abstract":"<div><div>The constant growth of DNNs makes them challenging to implement and run efficiently on traditional compute-centric architectures. Some accelerators have attempted to add more compute units and on-chip buffers to solve the memory wall problem without much success, and sometimes even worsening the issue since more compute units also require higher memory bandwidth. Prior works have proposed the design of memory-centric architectures based on the Near-Data Processing (NDP) paradigm. NDP seeks to break the memory wall by moving the computations closer to the memory hierarchy, reducing the data movements and their cost as much as possible. The 3D-stacked memory is especially appealing for DNN accelerators due to its high-density/low-energy storage and near-memory computation capabilities to perform the DNN operations massively in parallel. However, memory accesses remain as the main bottleneck for running modern DNNs efficiently.</div><div>To improve the efficiency of DNN inference we present QeiHaN, a hardware accelerator that implements a 3D-stacked memory-centric weight storage scheme to take advantage of a logarithmic quantization of activations. In particular, since activations of FC and CONV layers of modern DNNs are commonly represented as powers of two with negative exponents, QeiHaN performs an implicit in-memory bit-shifting of the DNN weights to reduce memory activity. Only the meaningful bits of the weights required for the bit-shift operation are accessed. Overall, QeiHaN reduces memory accesses by 25% compared to a standard memory organization. We evaluate QeiHaN on a popular set of DNNs. On average, QeiHaN provides <span><math><mrow><mn>4</mn><mo>.</mo><mn>3</mn><mi>x</mi></mrow></math></span> speedup and <span><math><mrow><mn>3</mn><mo>.</mo><mn>5</mn><mi>x</mi></mrow></math></span> energy savings over a Neurocube-like accelerator.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"159 ","pages":"Article 103320"},"PeriodicalIF":3.7,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143133687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Input/mapping precision controllable digital CIM with adaptive adder tree architecture for flexible DNN inference

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2024.103327

Juhong Park, Johnny Rhe, Chanwook Hwang, Jaehyeon So, Jong Hwan Ko

{"title":"Input/mapping precision controllable digital CIM with adaptive adder tree architecture for flexible DNN inference","authors":"Juhong Park, Johnny Rhe, Chanwook Hwang, Jaehyeon So, Jong Hwan Ko","doi":"10.1016/j.sysarc.2024.103327","DOIUrl":"10.1016/j.sysarc.2024.103327","url":null,"abstract":"<div><div>Digital compute-in-memory (CIM) systems, known for their precise computations, have emerged as a viable solution for real-time deep neural network (DNN) inference. However, traditional digital CIM systems often suffer from suboptimal array utilization due to static multi-bit input/mapping dataflows and inflexible adder tree structures, which do not adequately accommodate the diverse computational demands of DNNs. In this paper, we introduce a novel digital CIM architecture that dynamically redistributes bit precisions across the input and mapping domains according to computational load and data precision, thereby improving array utilization and energy efficiency. For supporting flexible bit configurations, the system incorporates an adaptive adder tree with the integrated bit-shift logic. To minimize potential overhead introduced by the bit-shiftable adder tree, we also propose a grouping algorithm that efficiently executes shift and add operations. Simulation results show that our proposed methods not only improve array utilization but also significantly accelerate computation speed, achieving up to a 10.46<span><math><mo>×</mo></math></span> speedup compared to traditional methods.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"159 ","pages":"Article 103327"},"PeriodicalIF":3.7,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143133735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimizing the performance of in-memory file system by thread scheduling and file migration under NUMA multiprocessor systems

IF 3.7 2区计算机科学

Journal of Systems Architecture Pub Date : 2025-02-01 DOI: 10.1016/j.sysarc.2025.103344

Ting Wu , Jingting He , Ying Qian , Weichen Liu

{"title":"Optimizing the performance of in-memory file system by thread scheduling and file migration under NUMA multiprocessor systems","authors":"Ting Wu , Jingting He , Ying Qian , Weichen Liu","doi":"10.1016/j.sysarc.2025.103344","DOIUrl":"10.1016/j.sysarc.2025.103344","url":null,"abstract":"<div><div>Internet and IoT Applications generate large amounts of data that require efficient storage and processing. Emerging Compute Express Link (CXL) and Non-Volatile Memories (NVM) bring new opportunities for in-memory computing by reducing the latency of data access and processing. Many in-memory file systems based on the Hybrid DRAM/NVM are designed for high performance. However, achieving high performance under Non-Uniform Memory Access (NUMA) multiprocessor systems has significant challenges. In particular, the performance of file requests on NUMA systems varies over a disturbingly wide range, depending on the affinity of threads to file data. Moreover, memory controllers and interconnect links congestion bring excessive latency and performance loss on file accesses. Therefore, both the placement of file and thread and load balance are critical for data-intensive applications on NUMA systems. In this paper, we optimize the performance of multiple threads requesting in-memory files on NUMA systems by considering both memory congestion and data locality. First, we present the system model and formulate the problem as latency minimization on NUMA nodes. Then, we present a two-layer design to optimize the performance by properly migrating threads and dynamically adjusting the file distribution. Further, based on the design, we implement a functional NUMA-aware in-memory file system, Hydrafs-RFCT, in the Linux kernel. Experimental results show that the Hydrafs-RFCT optimizes the performance of multi-thread applications on NUMA systems. The average aggravated performance of Hydrafs-RFCT is 100.14 %, 112.7 %, 39.4 %, and 6.4 % higher than that of Ext4-DAX, PMFS, SIMFS, and Hydrafs, respectively.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"159 ","pages":"Article 103344"},"PeriodicalIF":3.7,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143133625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0