发布求助
文献互助 智能选刊 最新文献

Norchip 2007最新文献

筛选
英文 中文
Fast mode decision for H.264 based on correlation between macroblocks 基于宏块间相关性的H.264快速模式决策
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481071
Bin Zhan, Baochun Hou, R. Sotudeh
{"title":"Fast mode decision for H.264 based on correlation between macroblocks","authors":"Bin Zhan, Baochun Hou, R. Sotudeh","doi":"10.1109/NORCHP.2007.4481071","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481071","url":null,"abstract":"The latest video coding standard, H.264/AVC, surpasses the former standards in performance by adopting several advanced techniques. One of the most notable improvements is flexible block types based rate distortion optimal mode decision (MD), which extremely enhances the video coding efficiency. However, the exhaustive MD involves remarkably computational complexity. Significantly increased consumption of encoding time and power leads to difficulty for actual applications. In this paper, a novel fast MD scheme is presented according the correlation between macroblocks. Sufficient experimental results show that the proposed scheme is able to reduce 44.79% encoding time averagely. The decrease of encoding performance in terms of PSNR and bitrate is acceptable.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123441118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Region-based routing algorithm for Network-on-Chip architectures 片上网络架构中基于区域的路由算法
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481043
T. Schonwald, O. Bringmann, W. Rosenstiel
{"title":"Region-based routing algorithm for Network-on-Chip architectures","authors":"T. Schonwald, O. Bringmann, W. Rosenstiel","doi":"10.1109/NORCHP.2007.4481043","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481043","url":null,"abstract":"In this paper, we present a novel approach for a region-based extension for a fully adaptive and fault-tolerant routing algorithm for Network-on-Chips (NoCs) called Force-Directed Wormhole Routing (FDWR) [T. Schonwald et al., 2007]. The proposed extension for the FDWR reduces the size of the routingtable of a switch and therefore the hardware costs. Despite the region-based extension the FDWR can be used for different NoC topologies like mesh, torus, and hypercube. The region-based extension is integrated into the Transaction Level Model (TLM) of the switch. We show how the proposed extension for the FDWR reduces the size of the routingtable. Simulation results depict that the traffic is distributed uniformly across the entire network despite the region-based extension. Furthermore, it is shown that in case of faulty switches the area around that switches is not overloaded and that the traffic is uniformly distributed across the entire network.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128474498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A low-voltage fully differential constant signal behavior rail-to-rail input stage in 0.12μm CMOS 一种0.12μm CMOS的低压全差分常数信号行为轨对轨输入级
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481037
W. Yan, H. Zimmermann
{"title":"A low-voltage fully differential constant signal behavior rail-to-rail input stage in 0.12μm CMOS","authors":"W. Yan, H. Zimmermann","doi":"10.1109/NORCHP.2007.4481037","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481037","url":null,"abstract":"This paper introduces a new fully differential low- voltage rail-to-rail input structure, which possesses a constant large- and small-signal behavior over the entire input common- mode range, and is suitable for low supply voltage applications in deep-submicron technologies. The proposed input stage is fabricated with two different opamp architectures in pure digital 0.12mum CMOS technology for experimental verification. At plusmn0.5V supply, the gm-variation is only 5.45%. The slew-rate+/- deviation is 3.5/3.2%. The maximum current for signal behavior regulation is reduced down to 90 mum.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129545731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sizing of MOS device in LC-tank oscillators LC-tank振荡器中MOS器件的尺寸
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481046
Jian Chen, F. Jonsson, Lirong Zheng, H. Tenhunen, Dian Zhou
{"title":"Sizing of MOS device in LC-tank oscillators","authors":"Jian Chen, F. Jonsson, Lirong Zheng, H. Tenhunen, Dian Zhou","doi":"10.1109/NORCHP.2007.4481046","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481046","url":null,"abstract":"Since previous publications show conflicting results about sizing device, relationship between device size and 1/f2 phase noise is studied and closed-form equations are derived in order to help designers to size devices in LC-tank oscillators for good phase noise performance. The analysis is divided into two steps. Firstly, periodic noise transfer functions of each VCO noise source to the output of switch FETs are derived, and the impact of sizing on these functions is discussed. Secondly, phase noise equations are derived with these functions. Experiments show that phase noise predicted by the equations agrees with that from simulations.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130652687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Performance analysis of BMC and Decision Units in the differential analog Viterbi decoder 差分模拟维特比解码器中BMC和决策单元的性能分析
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481027
J. Maunu, M. Laiho, A. Paasio
{"title":"Performance analysis of BMC and Decision Units in the differential analog Viterbi decoder","authors":"J. Maunu, M. Laiho, A. Paasio","doi":"10.1109/NORCHP.2007.4481027","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481027","url":null,"abstract":"In modern high-speed telecommunication systems a direct analog approach enables the A/D converter to be excluded from the Viterbi decoder implementation and avoids the speed bottlenecks in digital computation. The differential structure eliminates the need for the conventional trace-back memory thus enabling on-line decoding after initial transitional stages. This paper presents the circuit level analysis of branch metric calculation and decision units for a differential analog Viterbi decoder addressed to a (2,1,7) convolutional code. The speed and power consumption in these units is simulated with 0.13 mum CMOS technology. Further, the impact of inaccuracies in these units on the decoder performance is estimated.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130478171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
LMS-based identification and compensation of timing mismatches in a two-channel time-interleaved analog-to-digital converter 基于lms的双通道时间交错模数转换器时序失配辨识与补偿
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481041
S. Saleem, C. Vogel
{"title":"LMS-based identification and compensation of timing mismatches in a two-channel time-interleaved analog-to-digital converter","authors":"S. Saleem, C. Vogel","doi":"10.1109/NORCHP.2007.4481041","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481041","url":null,"abstract":"A time-interleaved ADC (TIADC) increases the overall sampling rate by combining multiple slow ADCs. However, the performance of a TIADC suffers from several mismatches such as time, offset, and gain mismatches. This paper deals with the identification and compensation of timing mismatches in a TIADC using the least mean square (LMS) algorithm. The method only requires a bandlimited and oversampled input signal. We present a detailed discussion and demonstrate the effectiveness of the proposed method by numerical simulations.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114238233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Low power tunable CMOS I-UWB transmitter design 低功率可调CMOS I-UWB发射机设计
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481052
D. Sarmiento, M. Nejad, H. Tenhunen, Lirong Zheng
{"title":"Low power tunable CMOS I-UWB transmitter design","authors":"D. Sarmiento, M. Nejad, H. Tenhunen, Lirong Zheng","doi":"10.1109/NORCHP.2007.4481052","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481052","url":null,"abstract":"In this paper an on-chip tunable Impulse-Ultra Wide Band Transmitter is presented. It is capable of modifying the power emission to comply with the FCC regulations at different pulse rates up to 300 MHz using two external controls. The maximum power consumption is 1.2 mW and 142 muW at 300 MHz and 10 MHz PRF respectively with a leakage current of 100 nA. The prototype has been designed in 0.18 UMC technology and placed in a QFN lead-less package.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116220360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
FPGA-based CRAIMOT basis function generator 基于fpga的CRAIMOT基函数生成器
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481076
P. Misans, M. Terauds, G. Valters, U. Derums, N. Vasilevskis
{"title":"FPGA-based CRAIMOT basis function generator","authors":"P. Misans, M. Terauds, G. Valters, U. Derums, N. Vasilevskis","doi":"10.1109/NORCHP.2007.4481076","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481076","url":null,"abstract":"This paper deals with the aspects of practical generation of basis function(s) (BF(s)) and the basic notions for orthonormal parametrical transform called as \"constant rotation angle in matrix orthonormal transform\" (CRAIMOT). The presented CRAIMOT BF generator is implemented as Altera's Cyclone II FPGA. A simplified block diagram and parameters of the generator are provided. The generator has a parallel structure and 5 times shorter sample time in opposite to the previous implementation. The sine/cosine former of BF generator has 3 different versions - CORDIC based, the linear interpolation based, and RAM table based. The comparison of the mentioned versions is provided.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116559098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Seven subthreshold flip-flop cells 七个阈下触发器细胞
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481061
Havard Pedersen Alstad, S. Aunet
{"title":"Seven subthreshold flip-flop cells","authors":"Havard Pedersen Alstad, S. Aunet","doi":"10.1109/NORCHP.2007.4481061","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481061","url":null,"abstract":"For ultra-low-power applications, operating the transistors in their subthreshold region is an effective way of reducing the power dissipation of a circuit. This paper presents a comparative study of the performance of seven D-flip-flop cells operating in the subthreshold region, based on simulations in a 90 nm CMOS technology. Simulations have been performed with a supply voltage ranging from 150 mV to 350 mV. The best PDP and EDP numbers at 175 mV is 13 aJ and 10 yJs, respectively.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123744662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Modeling A Code-Division Multiple-Access Network-on-Chip using SystemC 基于SystemC的码分多址片上网络建模
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481045
Xin Wang, J. Nurmi
{"title":"Modeling A Code-Division Multiple-Access Network-on-Chip using SystemC","authors":"Xin Wang, J. Nurmi","doi":"10.1109/NORCHP.2007.4481045","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481045","url":null,"abstract":"A systemC model of a code-division multiple- access (CDMA) network-on-chip (NoC) is presented in this paper. The CDMA NoC modeled in this paper is a globally- asynchronous locally-synchronous (GALS) on-chip communication network which applies CDMA technique to transfer data among different network nodes concurrently. The presented SystemC model uses Transaction-Level Modeling (TLM) approach to model the asynchronous handshake processes for data transfers in the CDMA NoC. A performance- estimation method which bases on timing back-annotation is also presented for exploring the CDMA NoC performance under different configurations in a fast and efficient way. Finally, the performance estimation results of the CDMA NoC with different configurations and traffic patterns are presented.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132610094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书