七个阈下触发器细胞

Norchip 2007 Pub Date : 2007-11-01 DOI:10.1109/NORCHP.2007.4481061

Havard Pedersen Alstad, S. Aunet

{"title":"七个阈下触发器细胞","authors":"Havard Pedersen Alstad, S. Aunet","doi":"10.1109/NORCHP.2007.4481061","DOIUrl":null,"url":null,"abstract":"For ultra-low-power applications, operating the transistors in their subthreshold region is an effective way of reducing the power dissipation of a circuit. This paper presents a comparative study of the performance of seven D-flip-flop cells operating in the subthreshold region, based on simulations in a 90 nm CMOS technology. Simulations have been performed with a supply voltage ranging from 150 mV to 350 mV. The best PDP and EDP numbers at 175 mV is 13 aJ and 10 yJs, respectively.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"Seven subthreshold flip-flop cells\",\"authors\":\"Havard Pedersen Alstad, S. Aunet\",\"doi\":\"10.1109/NORCHP.2007.4481061\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For ultra-low-power applications, operating the transistors in their subthreshold region is an effective way of reducing the power dissipation of a circuit. This paper presents a comparative study of the performance of seven D-flip-flop cells operating in the subthreshold region, based on simulations in a 90 nm CMOS technology. Simulations have been performed with a supply voltage ranging from 150 mV to 350 mV. The best PDP and EDP numbers at 175 mV is 13 aJ and 10 yJs, respectively.\",\"PeriodicalId\":448673,\"journal\":{\"name\":\"Norchip 2007\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Norchip 2007\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHP.2007.4481061\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Norchip 2007","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2007.4481061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 19

摘要

在超低功耗应用中，在晶体管的亚阈值区域工作是降低电路功耗的有效方法。本文基于90 nm CMOS技术的仿真，对工作在亚阈值区域的七个d触发器单元的性能进行了比较研究。在150 mV到350 mV的电源电压范围内进行了仿真。175 mV时的最佳PDP和EDP值分别为13 aJ和10 yJs。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Seven subthreshold flip-flop cells

For ultra-low-power applications, operating the transistors in their subthreshold region is an effective way of reducing the power dissipation of a circuit. This paper presents a comparative study of the performance of seven D-flip-flop cells operating in the subthreshold region, based on simulations in a 90 nm CMOS technology. Simulations have been performed with a supply voltage ranging from 150 mV to 350 mV. The best PDP and EDP numbers at 175 mV is 13 aJ and 10 yJs, respectively.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Norchip 2007

自引率

0.00%

发文量