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Linearized performance evaluation of polar transmitter for EDGE EDGE极性发射机的线性化性能评价
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481067
Yonghui Huang, T. Larsen
{"title":"Linearized performance evaluation of polar transmitter for EDGE","authors":"Yonghui Huang, T. Larsen","doi":"10.1109/NORCHP.2007.4481067","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481067","url":null,"abstract":"Polar transmitters are popular in today's mobile communications. Envelope and phase information are processed separately and restored at or before the RF power stage depending on the PA configuration. Key components of a typical polar transmitter include an envelope modulator, a phase modulator and a PA. Some technical challenges are described in this paper and some solutions are followed together with simulation results. In order to achieve higher power efficiency, a power supply modulated class-E PA is proposed as the power stage. The variation of the class-E power supply causes AM-AM and AM-PM distortions which must be linearized. Predistortion is a feasible solution to improve both envelope and phase linearization. PLL- based phase modulators potentially offer a higher degree of integration than mixer-based modulators since no SAW filter is required. The modulation bandwidth is expanded by a two- point phase modulator and the modulation accuracy is improved by the phase interpolation technique. This results in a so-called 3-point modulator.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114457365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Statistical analysis of steady state leakage currents in nano-CMOS devices 纳米cmos器件稳态泄漏电流的统计分析
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481069
J. Singh, J. Mathew, S. Mohanty, D. Pradhan
{"title":"Statistical analysis of steady state leakage currents in nano-CMOS devices","authors":"J. Singh, J. Mathew, S. Mohanty, D. Pradhan","doi":"10.1109/NORCHP.2007.4481069","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481069","url":null,"abstract":"Motivated by the problem of process variation in nano-scale CMOS, in this paper, we propose a multivariate statistical technique that uses the well known approach of principal component analysis (PCA), a technique extensively used in statistical modeling, to analyse the process variations. We use this approach to extract significant statistical information from the simulated data. We also propose a statistical model to characterize nano-scale CMOS device characteristics such as dynamic current Idyn, gate leakage Igate, and subthreshold leakage Isub considering the effects of random variations in the process and design parameters such as gate oxide thickness Tox, supply voltage Vdd and gate length L. These models can be used at higher level of circuit abstraction to study the design issues under process variation.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117282031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Surface charge detection probe 表面电荷探测探头
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481028
O. Kursu, J. Kivijakola, M. Pudas, T. Rahkonen
{"title":"Surface charge detection probe","authors":"O. Kursu, J. Kivijakola, M. Pudas, T. Rahkonen","doi":"10.1109/NORCHP.2007.4481028","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481028","url":null,"abstract":"This paper presents a low-cost contact mode surface charge probe that consists of an integrating IC, its control electronics and a metal probe. A microcontroller is used to control the probe and to A/D convert its analog output voltage. The measured object is moved by a translation stage that consists of three linear piezoactuators which are controlled by microcontrollers. The probe is calibrated by discharging a calibration capacitor into its input. The probe is used to scan the surface of an insulating material such as paper. The scans are done in normal air pressure. Charge transfer is found to occur due to both contact and break of the contact between the metal and the insulator. It is suspected that the frictional contact between the surface and the probe tip also cause charge transfer as well as charge differences on the insulator surface. Scan results from a paper surface are presented. The minimum detectable charge with the probe is approximately 100 fC.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129232911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An IEEE 754 floating point engine designed with an electronic system level methodlogy 采用电子系统级方法设计的ieee754浮点引擎
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481066
V. Chouliaras, J. Núñez-Yáñez
{"title":"An IEEE 754 floating point engine designed with an electronic system level methodlogy","authors":"V. Chouliaras, J. Núñez-Yáñez","doi":"10.1109/NORCHP.2007.4481066","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481066","url":null,"abstract":"This paper presents the design and implementation of an IEEE 754-compliant, single-precision, coarse-level pipelined floating point engine designed using a new Electronic System Level tool. The starting point was the Softfloat ANSI-C implementation of the standard. Minimal modifications, in the form of two parallel processes, were introduced to map the ANSI-C code to the Input/Output interface of a cardbus-based field-programmable gate array prototyping board. The remaining part of the code was directly synthesized to gates using Cebatech's C2R compiler and a number of configurations were studied with various degrees of functional-unit sharing and capabilities. Preliminary results clearly identify the potential of next generation ESL tools in transforming control-oriented applications written in ANSI-C code directly to synthesizable verilog, in record time. At the same time, the generated silicon exhibits up to two orders of magnitude better cycle performance compared to the Softfloat standard executing on an in-order superscalar processor (simulated) thus making a strong statement for the suitability of the ESL tool for the silicon synthesis of control-dominated applications. The design was validated both at the C-level as well as on an E14 PicoComputing FPGA board were it achieved an operating frequency of 64 MHz.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129347005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low complexity real-time feature extraction, using image projections 低复杂度的实时特征提取，使用图像投影
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481053
F. Kristensen, R. Cerviño, P. Nilsson, V. Owall
{"title":"Low complexity real-time feature extraction, using image projections","authors":"F. Kristensen, R. Cerviño, P. Nilsson, V. Owall","doi":"10.1109/NORCHP.2007.4481053","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481053","url":null,"abstract":"In this paper it is shown how low complexity image projections can be used to replace the much more memory demanding functions morphology and labeling. The image projections are intended to be used in an automatic real-time surveillance system to detect objects and extract features. The projection unit operates directly on the binary motion mask from the segmentation unit and can extract location, size and center of gravity of the detected objects. To increase the precision, multiple projections are calculated in the Y-direction of the motion mask. To verify the design a demonstrator has been implemented on a Xilinx FPGA, where the effect of different input settings can be evaluated in real-time. Compared to the previous solution with morphology and labeling, the memory requirement is reduced from O(n 2) to O(n).","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114079066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
AC characteristics of the MOSFET parasitic channel series resistances when absorbed into the current description 对MOSFET寄生通道串联电阻吸收时的交流特性进行描述
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481056
J. Saijets, J. Holmberg, M. Åberg
{"title":"AC characteristics of the MOSFET parasitic channel series resistances when absorbed into the current description","authors":"J. Saijets, J. Holmberg, M. Åberg","doi":"10.1109/NORCHP.2007.4481056","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481056","url":null,"abstract":"The AC behavior of absorbed parasitic series resistances of MOSFET models were compared to the conventional lumped resistance approach both theoretically and with real device values. The result suggested that absorbing the parasitic channel series resistances into the current description decreases the AC accuracy of the MOS model compared to conventional model with lumped resistances. Comparison were made with the input, output and gain and backward gain characteristics and it seems that the largest differences can be seen in the input and output behavior. The simple theoretical study of the two modeling approaches is confirmed by empirical comparisons of an 80 x 1.0 mum x 90 nm NMOS device characteristics up to 110 GHz.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127748020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 8-bit 10 kS/s 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities 8位10ks /s 0.18 μm CMOS SAR ADC，适用于具有传感功能的RFID应用
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481048
J. Marjonen, N. Pesonen, O. Vermesan, M. Åberg, A. Oja, H. Rustad, C. Rusu, P. Enoksson
{"title":"An 8-bit 10 kS/s 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities","authors":"J. Marjonen, N. Pesonen, O. Vermesan, M. Åberg, A. Oja, H. Rustad, C. Rusu, P. Enoksson","doi":"10.1109/NORCHP.2007.4481048","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481048","url":null,"abstract":"An 25-muW 1.8V 8-bit 10 kS/s successive approximation (SAR) analog to digital converter (ADC) was designed and fabricated in a 0.18 mum CMOS technology for passive UHF RFID applications. The resistive digital to analog converter (DAC) has no sample and hold block and can operate with low power consumption. The proposed comparator can operate at a low supply voltage. The measured total power consumption is 25 muW at a 10 kS/s conversion rate with a 1.8V single supply voltage.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130081202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ATtACk - A methodology for realizing partially reconfigurable FPGA systems 一种实现部分可重构FPGA系统的方法
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481039
G. Kulkarni, S. Chitti, A. Popp, Y. Le Moullec
{"title":"ATtACk - A methodology for realizing partially reconfigurable FPGA systems","authors":"G. Kulkarni, S. Chitti, A. Popp, Y. Le Moullec","doi":"10.1109/NORCHP.2007.4481039","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481039","url":null,"abstract":"Reconfigurable systems are expected to become more and more important as flexibility is becoming a requirement for many telecommunication applications. In this work, a methodology for handling dynamic partial reconfigurability is presented. The methodology builds on and extends the Rugby model and is applied to a case-study for implementation of two link-adaptation algorithms for WiMAX on a Xilinx Virtex-4 SX35 FPGA. The results indicate that implementation of dynamic partial reconfiguration can be handled well by the proposed methodology.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129381990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of different VDD-drives in ET & EER transmitters 不同vdd驱动器对ET和EER发射机的影响
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481031
T. Rautio, H. Harju, S. Hietakangas, T. Rahkonen
{"title":"Effects of different VDD-drives in ET & EER transmitters","authors":"T. Rautio, H. Harju, S. Hietakangas, T. Rahkonen","doi":"10.1109/NORCHP.2007.4481031","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481031","url":null,"abstract":"Envelope tracking (ET) technique transmitter employing a linear 0.5 W 1 GHz LDMOS PA (power amplifier) is studied. Four different methods for supply voltage modulation are discussed and measured results are given. Results show improvement both in efficiency and linearity when predistortion of the supply voltage is added. The same linear amplifier was used also in an envelope elimination and restoration (EER) system, and measurements show significant improvement in the linearity compared to the envelope tracking system, with no notable loss in the efficiency. Also the effect of feedthrough to the linearity was much lower than with a Class E PA in the same transmitter configuration.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129390779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Area efficient pseudo-parallel Galois field multipliers 面积效率伪平行伽罗瓦场乘法器
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481033
J. Mathew, Hafizur Rahaman, A. Jabir, D. Pradhan
{"title":"Area efficient pseudo-parallel Galois field multipliers","authors":"J. Mathew, Hafizur Rahaman, A. Jabir, D. Pradhan","doi":"10.1109/NORCHP.2007.4481033","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481033","url":null,"abstract":"This paper presents a new method for implementing Galois field multipliers over polynomial basis. The proposed method minimizes the number logic gates by reusing the same hardware. The proposed architecture can be adaptively resized according to the requirement, thereby giving more design flexibility. Design analysis based 0.18 micron technology shows that the proposed design with minimum latency is area/power efficient for finite field multipliers of size greater than 10.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131378810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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