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Design of A 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology 基于65nm CMOS技术的7位、200MS/s、2mW开关开环放大器的流水线ADC设计
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481042
C. Wulff, T. Ytterdal
{"title":"Design of A 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology","authors":"C. Wulff, T. Ytterdal","doi":"10.1109/NORCHP.2007.4481042","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481042","url":null,"abstract":"We present the design of a 7-bit 200 MS/s pipelined ADC with switched open-loop amplifiers in a 65 nm CMOS technology. As a result of turning off the open-loop amplifiers during sampling we reduce the power dissipation by 23%. The ADC achieves a SNDR of 40 dB close to the Nyquist frequency, with a power dissipation of 2 mW, which results in a Walden FOM of 0.13 pJ/step and a Thermal FOM of 1.6 fJ/step.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115691564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Translating behavioral VHDL for emulation 翻译行为VHDL为仿真
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481073
P. Ellervee, U. Reinsalu, A. Arhipov
{"title":"Translating behavioral VHDL for emulation","authors":"P. Ellervee, U. Reinsalu, A. Arhipov","doi":"10.1109/NORCHP.2007.4481073","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481073","url":null,"abstract":"Emulation is widely used to increase simulation speed. The main problem is that to map it into hardware, the description of the model must be synthesizable. This is not difficult for modules described at lower abstraction levels but almost impossible for behavioral descriptions when using traditional synthesis approaches. In this paper, an overview is given how to use behavioral synthesis principles to convert behavioral VHDL constructs into synthesizable ones. Differences between translation for synthesis and emulation are outlined.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115459092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A z-domain model and analysis of phase-domain all-digital phase-locked loops 相域全数字锁相环的z域模型及分析
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481030
S. Mendel, C. Vogel
{"title":"A z-domain model and analysis of phase-domain all-digital phase-locked loops","authors":"S. Mendel, C. Vogel","doi":"10.1109/NORCHP.2007.4481030","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481030","url":null,"abstract":"In this paper a comprehensive z-domain model of all-digital phase-locked loops (ADPLLs) is derived. The model accounts for phase and frequency signals and thus reflects both, frequency and phase behavior. The system model is investigated in detail. Each component is described in form of its transfer function to obtain an overall input/output behavior for the frequency and the phase domain. Furthermore, the physical characteristics of the noise sources within the structure are studied and their effects on the phase noise of the PLL are determined. The system level model is independent of the actual implementation, however, the relation to an existing frequency synthesizer for wireless communications is discussed. Simulation results confirm the accurateness of the presented model with respect to the time and frequency behavior of the system.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122318481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Defect tolerant ganged CMOS minority gate 缺陷容错组合CMOS少数栅极
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481060
A. Djupdal, P. Haddow
{"title":"Defect tolerant ganged CMOS minority gate","authors":"A. Djupdal, P. Haddow","doi":"10.1109/NORCHP.2007.4481060","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481060","url":null,"abstract":"Production defects, resulting in faulty transistors, provide a challenge for the semiconductor industry in terms of reduced Yield. As defect densities are expected to increase as the semi-conductor feature size decreases, some form of transistor level defect tolerance is desirable to reduce this increasing production challenge. This paper proposes a solution, based on the ganged CMOS minority gate, for transistor level defect tolerance for minority gates.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114238873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A method for measuring substrate noise in the UWB frequency band on lightly doped substrates 一种在轻掺杂基板上测量超宽带频带基板噪声的方法
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481057
M. Shen, T. Tong, J. Mikkelsen, T. Larsen
{"title":"A method for measuring substrate noise in the UWB frequency band on lightly doped substrates","authors":"M. Shen, T. Tong, J. Mikkelsen, T. Larsen","doi":"10.1109/NORCHP.2007.4481057","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481057","url":null,"abstract":"A measurement method for characterizing the substrate noise over the ultra-wideband (UWB) frequency band in UWB systems implemented using lightly doped CMOS processes is presented. The measurement structure in this method is based on modified ground-signal-ground (GSG) pads. In addition, the effects of the distance-based substrate resistance and the capacitive coupling between the substrate and the ground of the measurement setup are evaluated by on-wafer measurement of a test chip fabricated in a 0.18 mum lightly doped CMOS process. An equivalent circuit model of the presented measurement structure is given and shows accurate fit. From the measurement results the presented method is shown to provide a measurement band from 3 GHz to 10 GHz. To further validate the usability of the method a practical class-E PA is used.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115261008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Soft-error induced system-failure rate analysis in an SoC SoC中软错误引起的系统故障率分析
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481075
S. Tony, H. Mohammad, J. Mathew, D. Pradhan
{"title":"Soft-error induced system-failure rate analysis in an SoC","authors":"S. Tony, H. Mohammad, J. Mathew, D. Pradhan","doi":"10.1109/NORCHP.2007.4481075","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481075","url":null,"abstract":"This paper proposes an analytical method to assess the soft-error rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML model of the SoC and the raw soft-error rate of different parts of the platform as its inputs. Soft-errors on the design are modelled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. This Architectural Vulnerability Factor (AVF) and the raw soft-error rate of the components in the platform are used to compute the SER of cores. Furthermore, the SER and the severity of error in each core in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125435660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ADDA - A versatile development platform for AD-and DA- converters 一个用于模数转换器的通用开发平台
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481049
S. Signell
{"title":"ADDA - A versatile development platform for AD-and DA- converters","authors":"S. Signell","doi":"10.1109/NORCHP.2007.4481049","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481049","url":null,"abstract":"ADDA is a versatile development platform for AD- and DA-converters. It contains performance analysis algorithms for converters enabling the user to characterise converters and create data-sheets. The converters characterised are either simulated or real products. Currently characterisation and modelling of Nyquist converters are included with delta-sigma converters to follow in a future release. The platform, written in C-language, is free software released with the Gnu General Public License (GPL) and is freely available for all parties interested to contribute with models, analysis methods or measurement setups. New models of converters are easily included in the platform following included templates and the instructions in the README.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126571496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of polar transmitter imperfections on UTRA LTE uplink performance 极性发射机缺陷对UTRA LTE上行链路性能的影响
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481068
B. Priyanto, T. B. Sørensen, O. K. Jensen, T. Larsen, T. Kolding, P. Mogensen
{"title":"Impact of polar transmitter imperfections on UTRA LTE uplink performance","authors":"B. Priyanto, T. B. Sørensen, O. K. Jensen, T. Larsen, T. Kolding, P. Mogensen","doi":"10.1109/NORCHP.2007.4481068","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481068","url":null,"abstract":"The polar transmitter is an alternative RF transmitter architecture solution to achieve a high-efficiency power amplifier. In this paper the impact of polar transmitter imperfections on the UTRA long term evolution (LTE) link level performance is investigated. The most common imperfections in a polar transmitter are modelled, such as timing delay alignment and power amplifier non-idealities. Our approach is to analyze the relation between error vector magnitude (EVM) and link performance loss due to each imperfection. The results obtained are based on LTE uplink parameter settings and show that the most severe polar transmitter problem in LTE uplink is the timing delay alignment, especially for higher order modulation and coding scheme. Results also show that the EVM is a good direct measure to estimate the link level performance loss for various imperfections in the anticipated EVM range. For 16 QAM rate 3/4, an SNR loss of approximately 0.5 dB can be estimated by an EVM value of 8%.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130689873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Custom topology generation for network-on-chip 为片上网络定制拓扑生成
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481044
M.B. Stuart, J. Sparsø
{"title":"Custom topology generation for network-on-chip","authors":"M.B. Stuart, J. Sparsø","doi":"10.1109/NORCHP.2007.4481044","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481044","url":null,"abstract":"This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration around an initial topology. The tabu search has been modified from its normally encountered form to allow easier escaping from local minima. A number of synthetic benchmarks are used for tuning the parameters of both heuristics and for testing the quality of the solutions each heuristic produces. An analytical model is used to determine communication latencies in the network-on-chip.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133872207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A GaN HEMT power amplifier with variable gate bias for envelope and phase signals 一种用于包络和相位信号的可变门偏置GaN HEMT功率放大器
Norchip 2007 Pub Date : 2007-11-01 DOI: 10.1109/NORCHP.2007.4481050
Pieternella Cijvat, K. Tom, Michael Faulkner, H. Sjöland
{"title":"A GaN HEMT power amplifier with variable gate bias for envelope and phase signals","authors":"Pieternella Cijvat, K. Tom, Michael Faulkner, H. Sjöland","doi":"10.1109/NORCHP.2007.4481050","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481050","url":null,"abstract":"This paper describes the design, simulation and measurement of a GaN power amplifier suitable for envelope and phase signal combination. The low-frequency envelope signal is used to vary the gate (bias) voltage of the device, resulting in a pulse width modulated drain voltage, while modulation of supply voltage or current is avoided. The test circuit is implemented using a discrete GaN HEMT power amplifier and discrete surface-mount passive components assembled on a PCB. Measurements showed a maximum drain efficiency of 59% at 360 MHz, at an output power of 29 dBm. The output power as a function of the gate bias voltage varied between 3 and 29 dBm, with the drain efficiency varying between 6 and 59%.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131349534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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