Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481058
O. Viitala, J. Flak, S. Lindfors
{"title":"Modeling capacitive links for broadband inter-chip communication","authors":"O. Viitala, J. Flak, S. Lindfors","doi":"10.1109/NORCHP.2007.4481058","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481058","url":null,"abstract":"This paper presents the modeling of a close-proximity communication link with a lumped circuit representation. The inter-chip data transfer is performed via capacitive couplings between the top facing dies (flip-chip arrangement). The problems occuring in such a wireless communications are introduced. Based on three-dimensional (3D) electromagnetics (EM) simulations, a lumped circuit model for the capacitive link has been developed. The effect of cross-talk between adjacent channels is also considered in the model and discussed.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121806527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481051
B. Priyanto, T. B. Sørensen, O. K. Jensen, T. Larsem, T. Kolding, P. Mogensen
{"title":"A spectrum shaping technique to control spectrum emission of UTRA LTE user equipment","authors":"B. Priyanto, T. B. Sørensen, O. K. Jensen, T. Larsem, T. Kolding, P. Mogensen","doi":"10.1109/NORCHP.2007.4481051","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481051","url":null,"abstract":"For the UTRA long term evolution (LTE), the transmit signal spectrum must comply with stringent spectrum emission mask requirements because of very low guard band size for high spectral efficiency. Compared to e.g. WCDMA, the requirements are tightened, which calls for efficient user equipment (UE) transmitter design, to balance the tradeoff among performance and hardware complexity. In this paper a spectrum shaping technique suitable for LTE user equipment is proposed and evaluated. The key component of this technique is an inverse Chebyshev digital IIR filter which has maximally flat in the passband and sharp transition from passband to stopband. We compare this technique with the well-known time windowing method which offers low implementation complexity. We study the two techniques impact on both error vector magnitude (EVM) and spectrum emission for two different LTE system bandwidths and for various bandwidth allocations for the user. Results show that for wideband setting (10 MHz) both techniques are able to produce acceptable EVM values less than 0.2%. However, for narrowband setting (1.4 MHz), only digital filtering performs sufficiently well since the time windowing method fails when the window overlap size is greater than the cyclic prefix length.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127358162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481079
Xinpeng Xing, Zhihua Wang, Dongmei Li
{"title":"A low voltage high precision CMOS bandgap reference","authors":"Xinpeng Xing, Zhihua Wang, Dongmei Li","doi":"10.1109/NORCHP.2007.4481079","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481079","url":null,"abstract":"In this paper, a low voltage bandgap reference with high precision is presented. Utilizing current mode structure, the minimum voltage of the proposed bandgap circuit can be reduced to 900 mV. Compensated with VEB linearization technique, this bandgap reference can reach a temperature coefficient of 10 ppm/degC in the range from 0degC to 150degC. With 1.1-V supply voltage, the power is 47 uW and the PSRR is -55 dB at DC frequency. Occupying 0.186 mm2 chip area, this bandgap reference has been verified in UMC 0.18um mixed mode CMOS technology.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127416878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481064
B. Babaei, S. Mirzakuchaki
{"title":"High CMRR and low THD current-mode instrumentation amplifier using current inversion technique","authors":"B. Babaei, S. Mirzakuchaki","doi":"10.1109/NORCHP.2007.4481064","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481064","url":null,"abstract":"The current-mode instrumentation amplifier based on second-generation current conveyors (CCII) offers many benefits over conventional instrumentation amplifier architectures. It does not need any matched components to achieve high CMRR and its bandwidth is not gain-bandwidth product limited. Therefore, a wideband CMOS current conveyor has been used in this structure. HSPICE simulations have shown that its performance is quite satisfactory for wideband current-mode signal processing. Furthermore, CMRR enhancement technique of current-mode instrumentation amplifiers is discussed. In addition, composite conveyor techniques which improve the instrumentation amplifier performance are presented. The new simulated instrumentation amplifier provides approximately 44 dB of improvement on the high-frequency CMRR up to the 3-dB corner frequency and even higher. Also a THD of %0.6 has been achieved.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122613801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481034
Saeeid Tahmasbi Oskuii, P. G. Kjeldsberg
{"title":"Power optimized partial product reduction interconnect ordering in parallel multipliers","authors":"Saeeid Tahmasbi Oskuii, P. G. Kjeldsberg","doi":"10.1109/NORCHP.2007.4481034","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481034","url":null,"abstract":"When designing the reduction tree of a parallel multiplier, we can exploit a large intrinsic freedom for the interconnection order of partial products. The transition activities vary significantly for different internal partial products. In this work we propose a method for generation of power-efficient parallel multipliers in such a way that its partial products are connected to minimize activity. The reduction tree is designed progressively. A simulated annealing optimizer uses power cost numbers from a specially implemented probabilistic gate-level power estimator and selects a power-efficient solution for each stage of the reduction tree. VHDL simulation using ModelSim shows a significant reduction in the overall number of transitions. This reduction ranges from 15% up to 32% compared to randomly generated reduction trees and is achieved without any noticeable area or performance overhead.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"66 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116316927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481078
T. Teodósio, Leonel Sousa
{"title":"QCA-LG: A tool for the automatic layout generation of QCA combinational circuits","authors":"T. Teodósio, Leonel Sousa","doi":"10.1109/NORCHP.2007.4481078","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481078","url":null,"abstract":"Quantum-dot Cellular Automata (QCA) is a promising successor for CMOS transistor technology, while allowing the implementation of logic circuits using quantum devices, such as quantum dots or single domain nano magnets, a new set of tools must be developed to assist the design and implementation process. Examples of such tools are the QCADesigner for handmade layout and physical simulation, and also tools for majority logic optimization. Since no tool is available for assisting the QCA layout generation, we propose tool to automatically generate the layout of QCA circuits. This tool, designated by QCA-Layout Generator (QCA-LG), was integrated in a general QCA technology design flow, accepting the most used formats of the synthesis tools and producing the layout output according to the QCADesigner tool. Therefore, the layout of a logical circuit described in VHDL is automatically generated, and can be further optimized by hand and simulated using the QCADesigner. Examples of layouts automatic generated by the QCA-LG are presented for simple logical circuits, and are also compared with optimal layouts designed by hand.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481040
E. Laulainen, M. Kosunen, L. Koskinen, M. Paavola, K. Halonen
{"title":"Decimation filter for a low-power sensor-interface system","authors":"E. Laulainen, M. Kosunen, L. Koskinen, M. Paavola, K. Halonen","doi":"10.1109/NORCHP.2007.4481040","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481040","url":null,"abstract":"The presented decimator was designed to decimate a delta- sigma A/D-converter as part of a sensor-interface system for a three axis accelerometer. The sensor-interface system is designed with a very low power consumption target so the main design target for the decimator is also power consumption. Further, the area of the decimator part was a constraint limiting the design. The decimator uses three parallel filters for the x-, y- and z-axes, 12-bit output accuracy is used for each channel. The downsampling ratio is programmable and can be 16, 32, 64 ... 1024. All the 12-bit wide outputs from the 3 filters are fed to a parallel-to- serial converter that outputs the 36 bits in a serial form. The design was implemented with a 0.25 mum process as part of the sensor interface system chip, the area for the decimator was 0.259 mm2. Measured power consumption of decimator is between 0.1 muW and 5 muW depending on the used operation mode and voltage.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"100 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481065
Z. Baghchehsaraei, S. Kristiansson, F. Ingvarson, K. Jeppson
{"title":"Evaluation of active cancellation of substrate noise in mixed-signal ICs","authors":"Z. Baghchehsaraei, S. Kristiansson, F. Ingvarson, K. Jeppson","doi":"10.1109/NORCHP.2007.4481065","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481065","url":null,"abstract":"In mixed-signal integrated circuits interference between noisy and sensitive circuits is a serious problem. Active cancellation of this substrate coupled noise was proposed about a decade ago and has been claimed to be more efficient than passive decoupling (DC/capacitive grounding). Most of the previously presented papers have investigated active decoupling methods using simple, less accurate, resistive network models as the common substrate. In this paper two common active decoupling circuits (feedforward and feedback) have been investigated using an accurate substrate model based on z-parameters. Three different configurations of contacts have been investigated: 1. all the contacts are close to each other; 2. just guard bands are close to each other; and 3. when guard rings are implemented. Conclusions have been reached with the aid of theoretical and simulation based approaches. When distances between contacts are small, the level of suppressed noise highly depends on the type of active decoupling circuit. In this case, if backplane is floating there is an optimum op-amp gain which should be used in order to gain the minimum coupled noise level. Conversely, when distances are large, none of the mentioned effects have been noticed. When guard rings are in use instead of guard bands, regardless of the fact that overall noise level is better, simple DC grounding is preferred.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122641639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481072
Xi Zhu, J. Moritz, Yichuang Sun
{"title":"Design of a fourth-order continuous-time filter for UWB receivers","authors":"Xi Zhu, J. Moritz, Yichuang Sun","doi":"10.1109/NORCHP.2007.4481072","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481072","url":null,"abstract":"The design and implementation of a CMOS current- mode fourth-order Butterworth continuous-time leap-frog (LF) multiple loop feedback (MLF) lowpass filter is described. The filter is implemented using a fully-differential linear, low voltage and low power operational transconductance amplifier (OTA). PSpice simulations using a standard TSMC 0.18 mum CMOS process with 1.5 V power supply have shown that the cut-off frequency of the filter ranges from 240 MHz to 300 MHz and dynamic range is about 58 dB at 240 MHz of cut-off frequency. The power consumption of the filter is only from 22.3 to 55 mW. The total output noise density is about 390 nA/VHz.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"595 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123456758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Norchip 2007Pub Date : 2007-11-01DOI: 10.1109/NORCHP.2007.4481059
J. Alfredsson, S. Aunet
{"title":"D-latch for subthreshold floating-gate circuits exploiting threshold elements","authors":"J. Alfredsson, S. Aunet","doi":"10.1109/NORCHP.2007.4481059","DOIUrl":"https://doi.org/10.1109/NORCHP.2007.4481059","url":null,"abstract":"When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.","PeriodicalId":448673,"journal":{"name":"Norchip 2007","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126561063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}