2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献_第4页

An Automated and Centralized Data Generation and Acquisition System 一个自动化和集中的数据生成和采集系统

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665490

Majdi Richa, Jean-Christophe Prévotet, Mickaël Dardaillon, M. Mroué, A. Samhat

{"title":"An Automated and Centralized Data Generation and Acquisition System","authors":"Majdi Richa, Jean-Christophe Prévotet, Mickaël Dardaillon, M. Mroué, A. Samhat","doi":"10.1109/icecs53924.2021.9665490","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665490","url":null,"abstract":"Data Generation and Acquisition (DGA) has become a major requirement for data processing and subsequent information analysis, especially in data science, big data, and pattern recognition (which is a cornerstone of machine learning techniques). A synchronized hybrid data generation and acquisition system has major advantages over traditional counterparts given the mixed-mode nature of its input signals (digital and analog) being aligned with its output signals. The proposed DGA system, in addition to being hybrid and synchronous, is a single-board programmable, compact and fully automated open-source hardware/software instrumentation device. This paper details the design methodology, the hardware/software interface, the end-usage and the possible applications of the device. When high accuracy and consistent fidelity are key features of a specific pattern generation/acquisition system, bulky and expensive interconnected instruments become the main hiccup. The system we are presenting does not compromise between compactness, centralization and portability on one side and flexibility, accessibility and efficiency on the other side.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125101948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Low-Power Anomaly Detection and Classification System based on a Partially Binarized Autoencoder for In-Sensor Computing 基于部分二值化自编码器的传感器内计算低功耗异常检测与分类系统

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665479

P. Vitolo, G. Licciardo, L. D. Benedetto, R. Liguori, A. Rubino, D. Pau

{"title":"Low-Power Anomaly Detection and Classification System based on a Partially Binarized Autoencoder for In-Sensor Computing","authors":"P. Vitolo, G. Licciardo, L. D. Benedetto, R. Liguori, A. Rubino, D. Pau","doi":"10.1109/icecs53924.2021.9665479","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665479","url":null,"abstract":"This work proposes a new ultra low-power fault detection system, suitable for extreme edge or in-sensor computing. The system is composed of a hybrid HW/SW architecture: a hardware auto-encoder (AE) is always on at the edge for anomaly detection (AD), and of a software convolutional neural network (CNN) is activated only if the anomaly is detected for its classification. To achieve low area and energy requirements, the AE exploits an original partially binarization scheme, while the CNN shares the feature extraction module with the AE. The implementation of the AE on a Xilinx Artix-7 FPGA demonstrates that it is capable to manage in real-time sensors with a maximum Output Data Rate (ODR) of 365 kHz with a power dissipation of 122 mW. Best synthesis results with TSMC CMOS 65 nm standard cells show a power consumption of $138 mumathrm{W}/text{MHz}$ and an area occupation of 0.49 mm2 when real-time operations are set, enabling the possibility to integrate the complete HW accelerator in the auxiliary circuitry that typically equips inertial MEMS and on the same die. Comparisons with the current literature show that the proposed system obtains state-of-the-art performances in terms of accuracy and compactness.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125234608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

FPGA Implementations of Espresso Stream Cipher Espresso流密码的FPGA实现

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665568

Gani Kumisbek, N. Anandakumar, Mohammad S. Hashmi

{"title":"FPGA Implementations of Espresso Stream Cipher","authors":"Gani Kumisbek, N. Anandakumar, Mohammad S. Hashmi","doi":"10.1109/icecs53924.2021.9665568","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665568","url":null,"abstract":"Security of resource-constrained hardware devices, such as the devices in Internet of Things regime, must consider performance and area consumption metrics. One of the viable options for designing lightweight cryptography could be stream cipher. The stream ciphers are symmetric ciphers designed for resource-limited devices. In this paper, we implemented the Espresso stream cipher on the Xilinx Spartan-7 FPGA device. During our implementation, we considered four cases: basic implementation with a full-width input, serial implementation with an unpipelined (basic) algorithm, serial implementation with a pipelined algorithm, and parallel cases. According to the results received, the parallel version reached a throughput of 1778 Mbps and consumed 113 slices. The serial version with an unpipelined output had the least area consumption of 68 slices to achieve a throughput of 511 Mbps. Results of implemented design are then compared with other stream cipher implementations, namely, Grain, Trivium, and MICKEY. It is identified that, despite limited parallelization, the Espresso stream cipher has one of the lowest area consumption compared to other stream cipher implementations.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123867794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hybrid Fixed-point/Binary Convolutional Neural Network Accelerator for Real-time Tactile Processing 用于实时触觉处理的混合定点/二元卷积神经网络加速器

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665586

H. Younes, A. Ibrahim, M. Rizk, M. Valle

引用次数: 1

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study 面向随机计算的高能效多轨道结构:贝叶斯传感器融合案例研究

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665535

J. Belot, A. Cherkaoui, R. Laurent, L. Fesquet

引用次数: 0

Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range 自参数化混沌映射:一种提供宽混沌范围的硬件效率方案

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665500

P. Paul, Anur Dhungel, Maisha Sadia, Md Razuan Hossain, B. Muldrey, Md. Sakib Hasan

{"title":"Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range","authors":"P. Paul, Anur Dhungel, Maisha Sadia, Md Razuan Hossain, B. Muldrey, Md. Sakib Hasan","doi":"10.1109/icecs53924.2021.9665500","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665500","url":null,"abstract":"We present a general method called “self-parameterization” for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions than existing 1-D maps. A wide chaotic range is a desirable property as it strengthens the security feature by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterized scheme reduces the hardware cost by involving only one chaotic map that modulates its own control parameter at every iteration by passing the map's previous output through a simple linear transformation. The widening of chaotic range after adding self-parameterization is demonstrated on three classical map functions: logistic, tent, and sine. Two hardware-efficient self-parameterized schemes are presented: one for field-programmable gate array (FPGA) implementation and the other one for integrated circuit (IC) implementation. The chaotic performance of the proposed scheme is evaluated with bifurcation plots and three established chaotic entropy metrics including, Lyapunov exponent, correlation coefficient, and correlation dimension.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134254899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Memristor Based Frequency Switching in Bandpass Filters 带通滤波器中基于忆阻器的频率开关

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665525

S. Hadi, Rida Gadhafi, Zayed Ahmad, Maryam Ahli, Ali Mohammed, Maher AlQassab, W. Mansoor

引用次数: 0

A Power Switch Size Optimization Strategy for Multi-Switch DC-DC Converters 多开关DC-DC变换器电源开关尺寸优化策略

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665603

Samuele Fusetto, Elisabetta Moisello, F. Cannillo, P. Malcovati, E. Bonizzoni

引用次数: 0

EDM: A multiclassification support system to identify seizure type using K Nearest Neighbor EDM:一种多分类支持系统，使用K近邻来识别癫痫类型

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665565

Shiza Shakeel, Nihal Afzal, Gul Hameed Khan, N. Khan, M. Abid, M. B. Altaf

{"title":"EDM: A multiclassification support system to identify seizure type using K Nearest Neighbor","authors":"Shiza Shakeel, Nihal Afzal, Gul Hameed Khan, N. Khan, M. Abid, M. B. Altaf","doi":"10.1109/icecs53924.2021.9665565","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665565","url":null,"abstract":"Seizure type identification plays a pivotal part in the diagnosis and management of epileptic seizure disorder. Unfortunately, did not get much attention in past decades due to the unavailability of databases with seizure type marking. Seizure types not only assists the neurologist in deciding the correct drug and its dosage but precaution the epileptic patients about the seizure attack and its severity. In the recent past, a significant contribution has been made by applying machine and deep learning algorithms to the binary classification of generalized seizures. This work proposes and implements an early diagnostic and management (EDM) system to assist the neurologist in type identification (5-classes) of the seizure activity at run time and also features an interactive graphical user interface (GUI). In the GUI, temporal, spectral (along with source localization) and spatial plots can be viewed along with the seizure data classified based on its types. The system utilizes a discrete wavelet transform (DWT) and k-nearest neighbour, (KNN) based on feature extraction and classification, respectively. The system is validated using 31 patients' recordings from Temple University Hospital (TUH) EEG Database. Our system achieves a 5-class classification accuracy, sensitivity and specificity of 97.7%, 92.9%, and 98.7%, respectively, for patient-wise cross-validation.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123489759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Design Generator of Parametrizable and Runtime Configurable Constant False Alarm Rate Processors 一种可参数化和运行时可配置的恒虚警率处理器设计生成器

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665482

Marija L. Petrovic, Vladimir M. Milovanović

{"title":"A Design Generator of Parametrizable and Runtime Configurable Constant False Alarm Rate Processors","authors":"Marija L. Petrovic, Vladimir M. Milovanović","doi":"10.1109/icecs53924.2021.9665482","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665482","url":null,"abstract":"Constant false alarm rate (CFAR) algorithms are widely used in radar signal processing for object detection in cluttered and noisy environments and their fast hardware implementation is required in many of the real time applications. For that purpose, a parametrizable and runtime reconfigurable generator of CFAR detectors, featuring fully streaming I/O data interface, is captured inside Chisel hardware design language. Generator provides up to seven different CFAR algorithms available to choose from in compile time and throughout runtime configurability. Besides the algorithm choice, a wide range of settings, such as I/O data type and bit-widths, reference and guard window sizes, linear or logarithmic processing modes, edge handling methods, as well as some implementation specific parameters, are provided, hence enabling quick and efficient design space exploration. Several generator instances are tested and verified on a commercially-available FPGA board in conjunction with off-the-shelf radar transceivers thus proving that instances from the proposed peak detector generator can be effectively used whenever low latency processing performance is mandatory.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123595866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1