2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)最新文献

筛选
英文 中文
Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs sram内存计算中的字线整形技术分析
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665469
K.L.N. Prasad, Aditya Biswas, Joycee Mekie
{"title":"Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs","authors":"K.L.N. Prasad, Aditya Biswas, Joycee Mekie","doi":"10.1109/icecs53924.2021.9665469","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665469","url":null,"abstract":"In-memory computing (IMC) architectures have emerged as a promising alternative to deal with data-intensive applications. Proposals based on analog or digital IMC require multiple word lines to be activated for performing computation. Specifically, in wide SRAM IMC architectures, the word line pulse shaper circuits need to be carefully investigated as pulsewidth degradation affects multiple rows, resulting in incorrect output, loss in linearity in results, or degraded performance. This paper implements compares and contrasts multiple word line shaper proposals for a wide SRAM array. Detailed post-layout simulation results of $512times 256$ array show that for 1-bit analog dot product, the standard deviation is improved by 0.19×, 0.21×, 0.21× 0.15× for 1,4,8, and 16bit word respectively. Further, word line shaping techniques improve the access time and compute delay by 2.86× and 3×, respectively for $128times 256$ array.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Comparative Study of Switchable Capacitor Structures for LC Oscillators in a 28-nm Technology 28纳米工艺中LC振荡器可切换电容器结构的比较研究
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665608
Lantao Wang, Jonas Meier, R. Wunderlich, S. Heinen
{"title":"A Comparative Study of Switchable Capacitor Structures for LC Oscillators in a 28-nm Technology","authors":"Lantao Wang, Jonas Meier, R. Wunderlich, S. Heinen","doi":"10.1109/icecs53924.2021.9665608","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665608","url":null,"abstract":"Switchable capacitors (SC) are increasingly intensively used in modern LC oscillators, as they suffer less on the process variation in comparison to the conventional MOSFET-based varactors with the technology shrinking. In the design of an LC oscillator, the structure of the SC is carefully chosen because it serves as the main contributor to the overall quality factor of the LC tank that has a significant impact on the phase noise performance of the oscillator. In order to study the characteristics of recently popular SC structures, this paper introduces a design methodology using large-signal simulations, i.e. periodic steady-state (PSS) and periodic AC analysis (PAC), to better calculate the difference between on- and off-state capacitance as well as the quality factor. The influence of the structures of the SC on the performance of the LC oscillator is verified using a 10 GHz complementary class-B digitally controlled oscillator designed in a 28-nm CMOS technology.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125750024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Squarewave-Based Multi-Frequency Impedance Analyzer Based on the Heterodyne Architecture 基于外差结构的方波多频阻抗分析仪
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665624
Alireza Mesri, M. Sampietro, G. Ferrari
{"title":"A Squarewave-Based Multi-Frequency Impedance Analyzer Based on the Heterodyne Architecture","authors":"Alireza Mesri, M. Sampietro, G. Ferrari","doi":"10.1109/icecs53924.2021.9665624","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665624","url":null,"abstract":"This paper presents a custom chip in 180 nm TSMC CMOS process for fast multi-frequency impedance measurements on biological samples. It uses square waveforms for the excitation of the sample and demodulation to drastically reduce the required power consumption of the chip. Impedance inaccuracies given by the harmonics of square waves are avoided using a mixed-signal heterodyne structure with a proper selection of the excitation and demodulation frequencies. The system allows the simultaneous measurement of the impedance at two frequencies and of the DC current. The chip dissipates only 6 mW, including the delta-sigma analog-to-digital converter, and operates up to a frequency of 12 MHz.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125803007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computationally Light Algorithms for Tactile Sensing Signals Elaboration and Classification 触觉感知信号精化与分类的计算光算法
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665554
Youssef Amin, C. Gianoglio, M. Valle
{"title":"Computationally Light Algorithms for Tactile Sensing Signals Elaboration and Classification","authors":"Youssef Amin, C. Gianoglio, M. Valle","doi":"10.1109/icecs53924.2021.9665554","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665554","url":null,"abstract":"Tactile sensing systems require embedded processing to extract structured information in many application domains as prosthetics and robotics. In this regard, this paper proposes computationally light strategies to pre-process the sensor signals and extract features, feeding single layer feed-forward neural networks (SLFNNs) that proved good generalization performance keeping low the computational cost. We validate our proposal by integrating a tactile sensing system on a Baxter robot to collect and classify data from three objects of different stiffness. We compare different features extraction techniques and five SLFNNs to show the trade-off between generalization accuracy and computational cost of the whole processing unit. The results show that the processing unit that extracts the mean and standard deviation features from signals and adopts a fully connected neural network (FCNN) with 50 neurons and ReLu activation function achieves a high accuracy (94.4%) in the 3-class classification problem with a low computational cost, leading to the deployment on a resource-constrained device.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128174698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low Power, Low Noise and Reconfigurable Readout Circuit for Physiological Biomarkers 一种用于生理生物标志物的低功耗、低噪声和可重构读出电路
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665476
Angelito A. Silverio, Danny Wen-Yaw Chung, Leandro Silvério
{"title":"A Low Power, Low Noise and Reconfigurable Readout Circuit for Physiological Biomarkers","authors":"Angelito A. Silverio, Danny Wen-Yaw Chung, Leandro Silvério","doi":"10.1109/icecs53924.2021.9665476","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665476","url":null,"abstract":"This work presents the design and performance verification of an ultra-low power and low noise sensor front-end circuit for biopotential signal acquisition or biosensor interfacing. The circuit consists of an input switching matrix for selecting the input sensing mode, a high gain and high common-mode rejection ratio instrumentation amplifier incorporating a fully differential input/output stage built upon a second-generation current conveyor pair and a differential bandpass filter section for post amplification and band limiting. A current mode bandgap reference utilizing subthreshold MOS devices and tunable MOS pseudoresistors provides the biasing voltages that exhibit high power supply ripple rejection. The readout circuit core has a noise efficiency factor of 2.52 while exhibiting a high differential gain and common-mode rejection ratio of 91 dB and 154 dB, respectively. The circuit dissipates around $2 mu mathrm{W}$ of power under a single supply rail of 1V. The circuit has been designed using TSMC $0.18 mumathrm{m}$ technology whose model file parameters are obtained from MOSIS. The circuit finds application in either wearable or implantable devices.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131728073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
1-D Convolutional Neural Networks for Touch Modalities Classification 一维卷积神经网络在触觉模态分类中的应用
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665576
C. Gianoglio, E. Ragusa, R. Zunino, M. Valle
{"title":"1-D Convolutional Neural Networks for Touch Modalities Classification","authors":"C. Gianoglio, E. Ragusa, R. Zunino, M. Valle","doi":"10.1109/icecs53924.2021.9665576","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665576","url":null,"abstract":"Artificial tactile systems can facilitate the life of people suffering from a loss of the sense of touch. These systems use sensors and digital, battery-operated embedded units for data processing. Therefore, low-power, resource-constrained devices should host those embedded devices. The paper presents a framework based on 1-D convolutional neural networks (CNNs), which tackles the problem of classifying touch modalities, while limiting the number of architecture parameters. The paper also considers the computational cost of the pre-processing stage that handles tactile-sensor data before classification. The related pre-processing unit affects resources occupancy, computational cost, and ultimately classification accuracy. The experimental session involved a state-of-the-art real-world dataset containing three touch modalities. The 1-D CNN outperformed existing solutions in terms of accuracy, and showed a satisfactory trade-off between accuracy, computational cost, and resources occupancy. The implementation of the 1-D CNN classifier on an Arduino Nano 33 BLE device yielded real-time performances.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134466577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Simple, Versatile Integration Platform based on a Printed Circuit Board for Lab-on-a-Chip Systems 基于印刷电路板的芯片实验室系统简单通用集成平台
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665484
Simon Dallaire, Paul-Vahé Cicek
{"title":"A Simple, Versatile Integration Platform based on a Printed Circuit Board for Lab-on-a-Chip Systems","authors":"Simon Dallaire, Paul-Vahé Cicek","doi":"10.1109/icecs53924.2021.9665484","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665484","url":null,"abstract":"This work presents a novel process to embed an active silicon chip into a PCB for integrated microfluidic applications. The integration process is fast, affordable, and makes use of standard equipment and materials. It is ideal for quick prototyping but could also eventually be adapted for mass production since it is compatible with industrial technologies. A significant benefit of the proposed method is the ability to directly combine heterogeneous components, whether they be microfluidic, microelectromechanical, or electronic, within an integrated, compact system. This platform aims to serve as a further step towards realizing intelligent lab-on-a-chip systems.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133800891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep Learning Autoencoder-based Compression for Current Source Model Waveforms 基于深度学习自编码器的电流源模型波形压缩
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665573
W. Raslan, Y. Ismail
{"title":"Deep Learning Autoencoder-based Compression for Current Source Model Waveforms","authors":"W. Raslan, Y. Ismail","doi":"10.1109/icecs53924.2021.9665573","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665573","url":null,"abstract":"Modeling complex cell behavior is critical for accurate static timing analysis. Huge waveform data needed for current source models explodes technology file size and degrades design flow performance. We used deep learning nonlinear Autoencoders to compress voltage and current waveforms and compared them with singular component analysis approach. Autoencoders gave up to 3.37x compression ratio for voltage waveforms with average percentage error below 0.85% better than SVD approach. Autoencoders achieved 1.7x compression ratio for complex rising-edge current waveforms at model loss of 7.6e-5 and comparable results to SVD approach for the falling-edge waveforms. SVD remains more computationally efficient than Autoencoders.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115770189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Frequency-Interleaved ADC with RF Equivalent Ideal Filter for Broadband Optical Communication Receivers 宽带光通信接收机用射频等效理想滤波器的频率交织ADC
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665589
Ryo Kabeya, Y. Umeda, K. Takano
{"title":"Frequency-Interleaved ADC with RF Equivalent Ideal Filter for Broadband Optical Communication Receivers","authors":"Ryo Kabeya, Y. Umeda, K. Takano","doi":"10.1109/icecs53924.2021.9665589","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665589","url":null,"abstract":"To process an ultra-wideband signal with narrower-band analog-to-digital converters (ADCs), frequency-interleaved (FI) receiver technique that divides an ultra-broadband signal to narrower-band signals has been reported to date. Conventional FI ADCs use analog filters such as LC filters to divide an ultrawideband signal to separated narrower band signals. However, aliasing and level deviation of the signals that occurs in crossover frequency region of the filters degrades the signal transmission quality of the receivers that use FI ADCs. To mitigate this degradation digital signal processing technique to compensate the distortion due to the aliasing and level deviation has been reported. However, the compensation of the aliasing and level deviation need large-scale signal processing. In addition, degradation in signal transmission quality due to decrease in signal to noise ratio and distortion due to nonlinearity caused by the level deviation cannot be removed completely. To omit these degradations and improve the signal transmission quality we propose FI ADCs with an RF equivalent ideal filter (EIF). Computer simulation with ideal circuit components shows a potential to have an excellent band-separation capability and highly-accurate signal transmission quality without large-scale signal processing for the distortion compensation.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114560377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Structured Recurrent Neural Network Model Order Reduction for SISO and SIMO LTI Systems SISO和SIMO LTI系统的结构化递归神经网络模型降阶
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) Pub Date : 2021-11-28 DOI: 10.1109/icecs53924.2021.9665593
W. Raslan, Y. Ismail
{"title":"Structured Recurrent Neural Network Model Order Reduction for SISO and SIMO LTI Systems","authors":"W. Raslan, Y. Ismail","doi":"10.1109/icecs53924.2021.9665593","DOIUrl":"https://doi.org/10.1109/icecs53924.2021.9665593","url":null,"abstract":"Obtaining accurate and less computational demanding reduced models is a continuous challenge with complex systems. We propose a RNN network structure that can model LTI SISO systems of any order. Using this structured RNN model, a complex system of 598 states is reduced to a 10th order system at 9.04e-6 mean-square-error. SISO 4th order outperformed reported results of other MOR techniques. The RNN network structure is extended to model SIMO LTI of any number of output and any system order. Using this RNN SIMO network, RLC interconnect of 108 states was reduced to a 5th system at 9.1e-4 mean-square-error.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114917173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信