Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs

Abstract

In-memory computing (IMC) architectures have emerged as a promising alternative to deal with data-intensive applications. Proposals based on analog or digital IMC require multiple word lines to be activated for performing computation. Specifically, in wide SRAM IMC architectures, the word line pulse shaper circuits need to be carefully investigated as pulsewidth degradation affects multiple rows, resulting in incorrect output, loss in linearity in results, or degraded performance. This paper implements compares and contrasts multiple word line shaper proposals for a wide SRAM array. Detailed post-layout simulation results of $512\times 256$ array show that for 1-bit analog dot product, the standard deviation is improved by 0.19×, 0.21×, 0.21× 0.15× for 1,4,8, and 16bit word respectively. Further, word line shaping techniques improve the access time and compute delay by 2.86× and 3×, respectively for $128\times 256$ array.