{"title":"Hybrid Spintronics/CMOS Logic Circuits Using All-Optical-Enabled Magnetic Tunnel Junction","authors":"Surya Narain Dikshit;Arshid Nisar;Seema Dhull;Namita Bindal;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2022.3188768","DOIUrl":"10.1109/OJNANO.2022.3188768","url":null,"abstract":"Spintronics is one of the emerging fields for next-generation low power, high endurance, non-volatile, and area efficient memory technology. Spin torque transfer (STT), spin orbit torque (SOT), and electric field assisted switching mechanisms have been used to switch magnetization in various spintronic devices. However, their operation speed is fundamentally limited by the spin precession time that typically ranges in 10–400 ps. Such a time constraint severely limits the possible operation of these devices in high-speed systems. Optical switching using ultrashort laser pulses, on the other hand, is able to achieve sub-picosecond switching operation in magnetic tunnel junctions (MTJs). In this paper, all optically switched (AOS) MTJ has been used to design high speed and low power hybrid MTJ/CMOS based logic circuits such as AND/NAND, XOR/XNOR, and full adder. Owing to the ultra-fast switching operation of AOS-MTJ, the circuit level results show that the energy and speed of AOS-MTJ based logic circuits are improved by 85% and 97%, respectively, when compared to STT based circuits. In comparison to SOT based designs, the proposed logic circuits show 10% and 91% improvement in energy efficiency and speed, respectively.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"85-93"},"PeriodicalIF":1.7,"publicationDate":"2022-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9815875","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel Radiation Hardened SOT-MRAM Read Circuit for Multi-Node Upset Tolerance","authors":"Alok Kumar Shukla;Seema Dhull;Arshid Nisar;Sandeep Soni;Namita Bindal;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2022.3181040","DOIUrl":"10.1109/OJNANO.2022.3181040","url":null,"abstract":"The rapid transistor scaling and threshold voltage reduction pose several challenges such as high leakage current and reliability issues. These challenges also make VLSI circuits more susceptible to soft-errors, particularly when subjected to harsh environmental conditions. Hybrid spintronic/CMOS technology has emerged as one of the promising techniques to achieve low leakage power and non-volatility. Moreover, the spintronic memories are inherently resistant to the radiation effects such as heavy-ion irradiation and total ionizing dose. However, its CMOS peripheral circuitry is more susceptible to radiation-induced single-event upset (SEU) and double-node upset (DNU). In this paper, a new radiation-hardened read circuit for SOT magnetic random access memory (MRAM) on 45nm technology has been presented. The proposed circuit is highly resistant to all the probable SEUs and DNUs when compared to the previously reported designs. The results show that it can tolerate 4.5X, 11X, 9X, and 10.5X more critical charge as compared to the cross-coupled CMOS transistor, 11T, 13T, and 11T radiation hardened circuits, respectively. Moreover, the recovery time of the proposed circuit is improved by 20% when compared to cross-coupled CMOS transistor circuits.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"78-84"},"PeriodicalIF":1.7,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9791114","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Area Efficient Computing-in-Memory Architecture Using STT/SOT Hybrid Three Level Cell","authors":"Seema Dhull;Arshid Nisar;Rakesh Bhat;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2022.3166959","DOIUrl":"10.1109/OJNANO.2022.3166959","url":null,"abstract":"Spintronic-based computing-in-memory (CiM) architecture has emerged as one of the efficient solutions to counter the latency/bandwidth bottleneck of conventional von-Neumann architecture. However, computation within a small area while achieving low power consumption still remains a challenge. Multi-bit spintronic storage device is a suitable solution to improve the integration density of such architectures. This paper focuses on using spin-transfer torque (STT)/spin-orbit torque (SOT) based hybrid three-level cell (TLC) in CiM application for implementing logic circuits such as AND, XOR, and magnetic full adder (MFA). Moreover, the performance of the STT/SOT-TLC-based MFA is compared with other full adder designs. The results show that the proposed MFA is 75% more area-efficient in comparison to two-bit STT and SOT-based designs, and 50% more area-efficient in comparison to differential spin hall effect (DSHE) based designs","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"45-51"},"PeriodicalIF":1.7,"publicationDate":"2022-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9756330","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62887858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Akeeb Hassan;Sepehr Soroushiani;Abdulhameed Abdal;Sk Yeahia Been Sayeed;Wei-Chiang Lin;Markondeya Raj Pulugurtha
{"title":"Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications","authors":"Akeeb Hassan;Sepehr Soroushiani;Abdulhameed Abdal;Sk Yeahia Been Sayeed;Wei-Chiang Lin;Markondeya Raj Pulugurtha","doi":"10.1109/OJNANO.2022.3163386","DOIUrl":"10.1109/OJNANO.2022.3163386","url":null,"abstract":"Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"52-60"},"PeriodicalIF":1.7,"publicationDate":"2022-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9745373","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hilal Ahmad Bhat;Farooq Ahmad Khanday;Brajesh Kumar Kaushik;Faisal Bashir;Khurshed Ahmad Shah
{"title":"Quantum Computing: Fundamentals, Implementations and Applications","authors":"Hilal Ahmad Bhat;Farooq Ahmad Khanday;Brajesh Kumar Kaushik;Faisal Bashir;Khurshed Ahmad Shah","doi":"10.1109/OJNANO.2022.3178545","DOIUrl":"10.1109/OJNANO.2022.3178545","url":null,"abstract":"Quantum Computing is a technology, which promises to overcome the drawbacks of conventional CMOS technology for high density and high performance applications. Its potential to revolutionize today's computing world is attracting more and more researchers towards this field. However, due to the involvement of quantum properties, many beginners find it difficult to follow the field. Therefore, in this research note an effort has been made to introduce the various aspects of quantum computing to researchers, quantum engineers and scientists. The historical background and basic concepts necessary to understand quantum computation and information processing have been introduced in a lucid manner. Various physical implementations and potential application areas of quantum computation have also been discussed in this paper. Recent developments in each realization, in the context of the DiVincenzo criteria, including ion traps based quantum computing, superconducting quantum computing, nuclear magnetic resonance (NMR) quantum computing, spintronics and semiconductor based quantum computing have been discussed.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"61-77"},"PeriodicalIF":1.7,"publicationDate":"2022-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9783210","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ke Chen;Weiqiang Liu;Ahmed Louri;Fabrizio Lombardi
{"title":"Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation","authors":"Ke Chen;Weiqiang Liu;Ahmed Louri;Fabrizio Lombardi","doi":"10.1109/OJNANO.2022.3153329","DOIUrl":"https://doi.org/10.1109/OJNANO.2022.3153329","url":null,"abstract":"A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. At circuit level, power gating is initially utilized in the arithmetic modules to power off one of the modules (i.e., the exact module) when the inexact modules’ error is smaller than the threshold. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The proposed schemes have been implemented and tested for various applications (image and DCT processing). The results show that they can significantly reduce power consumption; moreover, the simulation results show that the Mean Square Error (MSE) at the proposed schemes’ output is low.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"36-44"},"PeriodicalIF":1.7,"publicationDate":"2022-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9680797/09720147.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3477918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"2022 Index IEEE Open Journal of Nanotechnology Vol. 3","authors":"","doi":"10.1109/OJNANO.2023.3234525","DOIUrl":"10.1109/OJNANO.2023.3234525","url":null,"abstract":"Presents the 2022 author/subject index for this issue of the publication.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"244-250"},"PeriodicalIF":1.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10007541","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62889352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transient Analysis of Hybrid Cu-CNT On-Chip Interconnects Using MRA Technique","authors":"Amit Kumar;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2021.3138344","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3138344","url":null,"abstract":"This paper presents the transient analysis of the equivalent single conductor (ESC) model of hybrid Cu-CNT on-chip interconnects for nanopackaging using matrix rational approximation (MRA) modeling technique. The analysis of propagation delay and peak crosstalk noise is carried out for single and coupled Cu-CNT interconnect lines at 14 nm and 22 nm technology nodes. It has been observed that the proposed MRA model provides a speed-up factor of 131 compared to the HSPICE. An error of less than 1% confirms the accuracy of the proposed model compared to the SPICE simulations. It is observed that Cu-CNT lines are more immune to the crosstalk due to lesser coupling effects compared to Cu and CNT interconnects. The efficacy, accuracy, and comprehensive analysis using the proposed model ensures immense application possibility of the proposed model in the VLSI design automation tools at the nanopackaging level.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"24-35"},"PeriodicalIF":1.7,"publicationDate":"2021-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9680797/09663009.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3514042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Attila Bonyar;Brajesh Kumar Kaushik;James E. Morris
{"title":"Guest Editorial: Nanopackaging Part I","authors":"Attila Bonyar;Brajesh Kumar Kaushik;James E. Morris","doi":"10.1109/OJNANO.2021.3134382","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3134382","url":null,"abstract":"This is the first of two Special Sections on Nanopackaging. This first one has appeared in OJ-NANO Vol. 2, 2021 and the second will appear in Vol. 3, 2022. Electronics packaging is a very multidisciplinary activity requiring an understanding of Electrical, Mechanical, Materials, Thermal (and Thermomechanical) Engineering, and of the underlying Physics and Chemistry. The papers in these two Special sections will reflect this diversity, and the application of modern mathematical algorithms and computational techniques to advance the engineering design techniques. Nanopackaging could refer to the packaging of possibly disruptive nanoelectronics technologies, and this would undoubtedly be a challenging and useful field, but so far, the term has been applied more to the application of nanotechnologies to microelectronics packaging. Although this is the case with some of the papers in this collection, two are particularly driven by the packaging needs of the continuation of Moore’s Law into advanced nanoscales.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"201-202"},"PeriodicalIF":1.7,"publicationDate":"2021-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09662658.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3515812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guanxuan Lu;Jiaqi Wang;Zhemiao Xie;John T. W. Yeow
{"title":"Carbon-Based THz Microstrip Antenna Design: A Review","authors":"Guanxuan Lu;Jiaqi Wang;Zhemiao Xie;John T. W. Yeow","doi":"10.1109/OJNANO.2021.3135478","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3135478","url":null,"abstract":"Increasing demands for high-speed wireless communication have stimulated the development of novel optoelectrical devices. Typically, terahertz (THz) wave, is much advantageous because of its relatively high-resolution transportation and strong penetrability property. One of the electromagnetic devices, the antenna, plays a key role in future THz devices. However, there are few review publishments related to carbon-based THz microstrip antenna designs. In this article, we list the basic figure of merits for evaluating antennas. We also show the developing microstrip antenna structures. Importantly, we summarize the current progress of THz microstrip antennas using different dimensional carbon materials, such as carbon nanotubes, graphene, and carbon foams. This review will lay a solid foundation for carbon-based THz microstrip antenna design, and furthermore provide novel sights for other THz antenna designs.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"15-23"},"PeriodicalIF":1.7,"publicationDate":"2021-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9680797/09652034.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3476147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}