2013 8th IEEE Design and Test Symposium最新文献

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Verification of multi decisional reactive agent using SMV model checker 用SMV模型检查器验证多决策反应剂
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727075
Abdelhay Haqiq, B. Bounabat
{"title":"Verification of multi decisional reactive agent using SMV model checker","authors":"Abdelhay Haqiq, B. Bounabat","doi":"10.1109/IDT.2013.6727075","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727075","url":null,"abstract":"On account of the evolution of technology, more complicated software arrives with the need to be verified to prevent the errors occurrence in a system which could generate fatal accidents and economic loss. These errors must be detected in an early stage during the development process to reduce redesign costs and faults. To ensure the correctness of software systems, formal verification provides an alternative approach to verify that an implementation of the expected system fulfills its specification. This paper focuses on the verification of reactive system behaviors specified by the Multi Decisional Reactive Agent (MDRA) and modeled using MDRA Profile. The objective in this paper is to use the Model Checking technique for MDRA Profile verification through the Model Checker SMV (Symbolic Model Verifier) to automatically verify the system properties expressed in temporal logic. The SMV mainly focusing on reactive systems provides a modular hierarchical descriptions and definition of reusable components. Besides, the expression of system properties is more described through both Computational Tree Logic (CTL) and Linear Temporal Logic (LTL).","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130787064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Liquid level monitoring using passive RFID tags 使用无源RFID标签进行液位监测
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727088
A. Atojoko, M. Bin-Melha, E. Elkazmi, M. Usman, R. Abd‐Alhameed, C. See
{"title":"Liquid level monitoring using passive RFID tags","authors":"A. Atojoko, M. Bin-Melha, E. Elkazmi, M. Usman, R. Abd‐Alhameed, C. See","doi":"10.1109/IDT.2013.6727088","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727088","url":null,"abstract":"Tank flooding have become major causes of pollution both in residential and industrial areas majorly caused by overflows of water(mostly residential) and volatile poisonous industrial liquids from the storage tanks. An effective way of avoiding this problem will be by deploying some mechanism to monitor liquid level at each point in time and escalating unusual liquid levelsto a pump control circuit or to the relevant authorities for prompt action to avoid a flooding occurrence. This paper presents a low cost power efficient liquid level monitoring technique. Passive RFID tags are designed modelled and deployed, the signal variation from the Alien Reader Software are used to effectively estimate the level of liquid in any surface or underground tank. The experimental set up is presented and an expository presentation is made of the passive tag design, modelled and simulated and adopted for same application.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132840648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Power constraints test scheduling of 3D stacked ICs 3D堆叠ic的功耗约束测试调度
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727115
S. Roy, Joya Sengupta, C. Giri, H. Rahaman
{"title":"Power constraints test scheduling of 3D stacked ICs","authors":"S. Roy, Joya Sengupta, C. Giri, H. Rahaman","doi":"10.1109/IDT.2013.6727115","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727115","url":null,"abstract":"Core based 3D stacked ICs (3D SICs) is an emerging area in today's semiconductor industry. Traditional testing approaches of 2D IC cannot be applied directly to 3D SICs. In this paper we have addressed a test scheduling approach that try to reduce the overall test application time (TAT) by optimizing the pre-bond and the post-bond test time while reckoning resource conflicts and satisfying power constraints. In addition we proposed distinct algorithms for wafer sort, partial overlapping in package test and rescheduling in package test. Experimental results show that our proposed approach achieved better reduced TAT compared to [1].","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A BIST method for TSVs pre-bond test 一种用于tsv粘结前测试的BIST方法
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727081
H. Zimouche, G. D. Natale, M. Flottes, B. Rouzeyre
{"title":"A BIST method for TSVs pre-bond test","authors":"H. Zimouche, G. D. Natale, M. Flottes, B. Rouzeyre","doi":"10.1109/IDT.2013.6727081","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727081","url":null,"abstract":"In this paper we present a Built-In-Self-Test (BIST) method dedicated to pre-bond testing of TSVs in 3D stacked integrated circuits. The test method aims to detect full-open and pin-hole defects by measuring the discharge delay of TSVs' equivalent capacitance. The paper presents an original solution for monitoring the discharge delay of the TSV under test independently of the process variations. Simulation-based results shows that the method is robust w.r.t these variations. The proposed BIST circuitry is small enough to be inserted in the available area between the TSVs.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114781905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity 部分电阻缺陷和偏置温度不稳定性对SRAM解码器可靠性的影响
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727124
Seyab Khan, M. Taouil, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor
{"title":"Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity","authors":"Seyab Khan, M. Taouil, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor","doi":"10.1109/IDT.2013.6727124","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727124","url":null,"abstract":"Partial open defects in modern Static Random Access Memory (SRAM) address decoders are one of the main causes of small delays; these are hard to detect and may result in escapes and reliability problems. In addition, Aging failures - such as Bias Temperature Instability (BTI)-may worsen the situation and accelerate the degradation (i.e. increase the delay) and cause sooner field failures. This paper investigates the impact of partial opens and BTI in SRAM address decoders first separately and thereafter in a combined manner. Simulation results show that BTI impact strongly depends on the selected worldline, transistor location and addressing scheme; and it cause up to 14.27% additional delay. In addition, they show that partial opens, which do not cause hard faults and allow memory operations to pass correctly, contribute up to 23.65% additional delay. Combining these failure mechanisms reveals that the degradation can strongly be worsened and accelerate wear-out; an additional delay of up to 31.20% can be caused. This indicates the importance of incorporating appropriate design-for-reliability/testability schemes in order to guarantee the required lifetime of the memory system.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134258658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs 优化3D堆叠ic的部分堆叠/完全堆叠测试架构
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727114
S. Roy, C. Giri, H. Rahaman
{"title":"Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs","authors":"S. Roy, C. Giri, H. Rahaman","doi":"10.1109/IDT.2013.6727114","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727114","url":null,"abstract":"Three-dimensional stacked ICs (3D SICs) are currently evolving as an area of great interest in modern semiconductor industry. Several partial stacks tests are required during 3D assembly because the die stacking steps and bonding may introduce defects. In this paper, we have addressed test architecture optimization for 3D stacked ICs implemented with hard dies under the TSV constraints. The main objective of our algorithm is to minimize the test time either for the testing of complete stack or complete stack and several partial stacks. Experimental results are performed for two handcrafted 3D SICs comprising of various system-on-chips from ITC'02 SOC test benchmarks.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134530078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Single-ended sense amplifier robustness evaluation for OxRRAM technology OxRRAM技术单端感测放大器鲁棒性评价
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727097
H. Aziza, M. Bocquet, M. Moreau, J. Portal
{"title":"Single-ended sense amplifier robustness evaluation for OxRRAM technology","authors":"H. Aziza, M. Bocquet, M. Moreau, J. Portal","doi":"10.1109/IDT.2013.6727097","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727097","url":null,"abstract":"In this paper, impact of OxRRAM cell variability on circuit performances is analyzed quantitatively at a circuit level. A single-ended sense amplifier architecture is evaluated against memory cell variability. This study enables enhancing OxRRAM yield as well as reducing cell consumption during a read operation without compromising reliability. Due to the stochastic nature of the switching process in OxRRAMs, leading to large variability, all simulations are Monte Carlo oriented.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121885250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Resource reservation technique for handover calls using integrated modeling technique 基于集成建模技术的交接呼叫资源预留技术
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727087
F. Onah, M. Ezeja, C. Ani
{"title":"Resource reservation technique for handover calls using integrated modeling technique","authors":"F. Onah, M. Ezeja, C. Ani","doi":"10.1109/IDT.2013.6727087","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727087","url":null,"abstract":"The increase in GSM mobile station (MS) density, without a corresponding increase in radio channel resource capacity, reduces the quality of service (QoS) standard provided to users. Attempts to improve the QoS standard usually leads to the creation of new base stations (BS) with the consequent reduction in the existing cell sizes. Although, the available network capacity is increased, this happens at the expense of increased numbers of call handoversSuch increase is usually accommodated by resource reservation. How well the reservation is made greatly influences the GSM network quality of service (QoS) and the general BS resource utilization. This work presents a radio channel resource reservation technique for GSM handover calls. A typical GSM network architecture was modeled using an integrated modeling technique in a MATLAB block oriented simulation environment. The analytical part of the model was developed using the Markov chain principle and validated using the existing popular Lee's queuing model. The relationships between the handover call blocking probability, fresh call blocking probability, the number of resources to be reserved and traffic intensity were established. Simulation results were analyzed and a method of determining the optimum number of resources that can be reserved for handover calls for a given BS resource capacity was presented.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124057103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An UHF RFID emulation platform with fault injection and real time monitoring capabilities 具有故障注入和实时监控功能的超高频RFID仿真平台
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727143
Omar Abdelmalek, D. Hély, V. Beroulle, I. Mezzah
{"title":"An UHF RFID emulation platform with fault injection and real time monitoring capabilities","authors":"Omar Abdelmalek, D. Hély, V. Beroulle, I. Mezzah","doi":"10.1109/IDT.2013.6727143","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727143","url":null,"abstract":"RFID tags are increasingly used for critical applications within harsh environments (aeronautics...) or for secure applications such as identification. However, such low cost systems, initially designed for non-critical applications with a high volume, are not robust by themselves. This paper presents the architecture and the implementation of an UHF RF Identification (RFID) tag emulation platform with fault injection and real time monitoring capabilities, which can help to validate such IC.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127256172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Opportunistic redundancy for improving reliability of embedded processors 提高嵌入式处理器可靠性的机会冗余
2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727090
Z. Wang, Renlin Li, A. Chattopadhyay
{"title":"Opportunistic redundancy for improving reliability of embedded processors","authors":"Z. Wang, Renlin Li, A. Chattopadhyay","doi":"10.1109/IDT.2013.6727090","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727090","url":null,"abstract":"The downscaling of technology features has brought the system developers an important design criteria, reliability, into prime consideration. Among reliability concerns, transient fault caused by external radiation effects and temperature gradients is becoming a significant factor for the erroneous execution of embedded processors. State-of-the-art reliability-aware design techniques for embedded processors are yet to take complete advantage of the instruction set and application knowledge. In this work, we present reliability protection techniques for embedded processors which opportunistically take advantage of the hardware redundancy. Several policies based on the reliability requirements from the applications are introduced to explore the reliability-performance trade-off. The efficiency of proposed techniques are demonstrated by using several embedded processors.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121143040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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