2013 8th IEEE Design and Test Symposium最新文献_第2页

Simulation and experimental verification: Dopant-free Si-nanowire CMOS technology on silicon-on-insulator material 模拟与实验验证:基于绝缘体上硅材料的无掺杂硅纳米线CMOS技术

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727098

U. Schwalke, Frank Wessely, Tillmann A. Krauss

引用次数: 0

Assertion based on-line fault detection applied on UHF RFID tag 基于断言的超高频RFID标签在线故障检测

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727091

I. Mezzah, O. Kermia, H. Chemali, Omar Abdelmalek, V. Beroulle, D. Hély

引用次数: 8

Compilation optimization exploration for thermal dissipation reduction in embedded systems 嵌入式系统降低散热的编译优化探索

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727121

Montassar Ben Saad, A. Jedidi, S. Niar, M. Abid

引用次数: 0

Energy-efficient truncated multipliers with scaling 节能截断乘法器与缩放

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727101

I. Abdelghany, W. Saab, Tarek Sakakini, Abdul-Amir Yassine, A. Chehab, A. Kayssi, I. Elhajj

引用次数: 2

Experimental evaluation of latency coding for gas recognition 延迟编码气体识别的实验评价

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727123

Jaber Hassan J. Al Yamani, F. Boussaïd, A. Bermak, D. Martinez

引用次数: 0

Energy efficient on-chip wireless interconnects with sleepy transceivers 节能的片上无线互连与休眠收发器

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727078

H. Mondal, Sujay Deb

{"title":"Energy efficient on-chip wireless interconnects with sleepy transceivers","authors":"H. Mondal, Sujay Deb","doi":"10.1109/IDT.2013.6727078","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727078","url":null,"abstract":"Both industry and academia has accepted Networks-on-Chip (NoCs) as the communication backbone for multi-core Systems-on-Chip (SoCs). But the traditional approach of implementing a NoC with planar metal interconnects has high latency and significant power consumption overhead. This is due to multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers. Wireless transceivers with power gating can significantly improve the energy efficiency of the interconnection network. In this paper we have implemented and evaluated sleep transistor based power-gated transceiver for low power on-chip wireless interconnects. This approach improved power saving for wireless communication up to 70% compared to existing wireless NoC. The transceiver consumes 36.8771 mA current while on and less than 9 nA while in sleep mode from 1 V power supply. The delay associated with this wireless transceiver is less than 10 ps.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122925591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Exploring test opportunities for memory and interconnects in 3D ICs 探索3D集成电路中存储器和互连的测试机会

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727132

M. Taouil, M. Lefter, S. Hamdioui

引用次数: 7

NOCBENCH: NOC synthesis benchmarks

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727134

O. Hammami, Xinyu Li

引用次数: 1

Efficient FPGA implementation of H.264 CAVLC entropy decoder H.264 CAVLC熵解码器的高效FPGA实现

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727116

A. Siblini, Elias Baaklini, Hassan Sbeity, A. Fadlallah, S. Niar

{"title":"Efficient FPGA implementation of H.264 CAVLC entropy decoder","authors":"A. Siblini, Elias Baaklini, Hassan Sbeity, A. Fadlallah, S. Niar","doi":"10.1109/IDT.2013.6727116","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727116","url":null,"abstract":"Multiprocessor-system-on-a-chip (MPSoC) is the dominating architecture in embedded systems. Applications need to be multi-threaded to benefit from the concurrency provided by the MPSoC. Many parallel versions of the new emerging H.264/AVC [1] already exist. However, providing a full parallel H.264 version is blocked by the fact that all parts of the decoder depend on the first sequential stage of the decoding process which is the entropy decoder (mainly CAVLC). The entropy decoder consumes about 30% [8] of the total time of the decoder. In this work, we propose an optimized FPGA design achieving the demands of multi-threaded H.264 decoder versions which can be integrated in an MPSoC. We focus in our work on time optimization and on cycle number decrease when decoding an encoded 4×4 block of pixels. We also aim to achieve a design that operates at high frequencies. The work leads to the ability to decode at least 62 frames per second for HD resolution 1280×720. Decoding takes 22 clock cycles for one block of 4×4 pixels at most. The design has an upper frequency limit of 247MHz. High resolutions frames such as 1920×1088 FHD (full high definition) video maintain a minimum frequency of 30 fps.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131319904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Automated flow for generating CMOS custom memory bit map between logical and physical implementation 用于在逻辑和物理实现之间生成CMOS自定义内存位图的自动化流程

2013 8th IEEE Design and Test Symposium Pub Date : 2013-12-01 DOI: 10.1109/IDT.2013.6727105

B. Mohammad, Nadeem Eleyan, Greg Seok, Hong Kim

引用次数: 1