2022 IEEE International Integrated Reliability Workshop (IIRW)最新文献

Impact of Single Defects on NBTI and PBTI Recovery in SiO2 Transistors 单缺陷对SiO2晶体管中NBTI和PBTI回收率的影响

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032748

K. Tselios, T. Knobloch, J. Michl, Dominic Waldhoer, C. Schleich, E. Ioannidis, H. Enichlmair, R. Minixhofer, T. Grasser, M. Waltl

{"title":"Impact of Single Defects on NBTI and PBTI Recovery in SiO2 Transistors","authors":"K. Tselios, T. Knobloch, J. Michl, Dominic Waldhoer, C. Schleich, E. Ioannidis, H. Enichlmair, R. Minixhofer, T. Grasser, M. Waltl","doi":"10.1109/IIRW56459.2022.10032748","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032748","url":null,"abstract":"The reliable operation of MOS transistors is affected by charge trapping at defects located inside the oxide and at the oxide/semiconductor interface. Each of the single defects can capture and emit a charge, alter the device electrostatics and thus affect the device behavior, which can be observed as a drift of the threshold voltage. Understanding the physical mechanisms of charge trapping and the dependencies of the threshold voltage drifts on the device parameters is crucial for reliable operation of modern transistors and the implementation of future technology nodes. An enhanced understanding can be developed by performing electrical measurements on nanoscale devices which allow to detect discrete steps in the measured drain current which correspond to emission events of charges, previously captured at single defects. Using measurements on large sets of devices, statistical distributions of step heights can be created to study the dependence of statistical quantities, like the link between the average threshold shift of a single emission event and the lateral device dimensions. From our measurements on commercial pMOS and nMOS devices we found that the dependence of the average step height on $W times sqrt L $ allows to describe the data accurately for a wide range of gate widths and lengths while the most widely used dependence on the device area fails to provide a good agreement.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121728254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Anomaly of NBTI data for PMOS transistors degraded by plasma processing induced charging damage (PID) 等离子体处理诱发充电损伤PMOS晶体管NBTI数据异常

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032757

Andreas Martin, Lukáš Valdman, Benjamin Hamilton Stafford, H. Nielen

引用次数: 2

Simulating and Modeling the Influence of Deep Trench Interface Recombination on Si Photodiodes 深沟槽界面复合对硅光电二极管影响的模拟与建模

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032736

Paul Stampfer, G. Meinhardt, T. Grasser, M. Waltl

{"title":"Simulating and Modeling the Influence of Deep Trench Interface Recombination on Si Photodiodes","authors":"Paul Stampfer, G. Meinhardt, T. Grasser, M. Waltl","doi":"10.1109/IIRW56459.2022.10032736","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032736","url":null,"abstract":"Deep Trench Isolation (DTI) is a common termination technique in optoelectronics to minimize cross-talk between single devices fabricated on the same chip. However, DTI can also affect the performance of optoelectronic devices. In this work we simulate and model the influence of minority carrier recombination at the DTI interface on the quantum efficiency, i.e. responsivity, of Si photodetectors. We demonstrate that DTI interface recombination is a non-linear effect with respect to the applied irradiance and causes a non-linear response of the photodetector, which must be avoided for certain applications. Furthermore, we show that sufficiently high positive or negative fixed oxide charges can improve device performance by reducing the DTI interface recombination. To maintain the benefit of electrical cross-talk minimization in combination with an almost linear responsivity we propose a structure terminated with lateral deep trench metal oxide semiconductor capacitors (DTMOSCAPs) to control the passivation of the DTI interface by an applied gate bias. By means of TCAD simulations, we show that such a device is superior to default DTI structures in terms of responsivity as well as linearity.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124574416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform 300mm晶圆平台上65nm CMOS集成纳米ReRAM器件失效分析

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032747

Maximilian Liehr, Jubin Hazra, K. Beckmann, N. Cady

引用次数: 1

Three Level Charge Pumping On Dielectric Hafnium Oxide Gate 介质氧化铪栅极上的三能级电荷泵送

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032750

Y. Raffel, M. Drescher, R. Olivo, M. Lederer, R. Hoffmann, L. Pirro, T. Chohan, T. Kämpfe, K. Seidel, S. De, J. Heitmann

引用次数: 2

Modeling Plasma-Induced Damage During the Dry Etching of Silicon 硅干蚀刻过程中等离子体诱导损伤的建模

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032764

Tobias Reiter, X. Klemenschits, L. Filipovic

引用次数: 0

Exploring Process-Voltage-Temperature Variations Impact on 4T1R Multiplexers for Energy-aware Resistive RAM-based FPGAs 探索工艺电压温度变化对能量感知电阻式ram fpga中4T1R多路复用器的影响

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032753

T. Rizzi, Andrea Baroni, A. Glukhov, D. Bertozzi, C. Wenger, D. Ielmini, C. Zambelli

引用次数: 1

Device Reliability to Circuit Qualification: Insights and Challenges 器件可靠性电路鉴定:见解和挑战

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10077885

F. Cacho, A. Bravaix, T. G. Seybou, H. Pitard, X. Federspiel, T. Kumar, F. Giner, A. Michard, D. Celeste, B. Miller, V. Dhanda, A. Varshney, V. Tripathi, J. Kumar

引用次数: 1

Ensuring robust ESD design with comprehensive reliability verification 通过全面的可靠性验证，确保稳健的ESD设计

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032761

K. Henderson, Brian Hulse, M. Styduhar, Peter Michelson

引用次数: 2

Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions 大范围应力条件下28nm CMOS技术晶体管老化模型的评估

2022 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2022-10-09 DOI: 10.1109/IIRW56459.2022.10032756

D. Sangani, J. Diaz-Fortuny, E. Bury, B. Kaczer, G. Gielen

引用次数: 3