Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)最新文献_第9页

GeneSys: a leaf-cell layout synthesis system for GHz VLSI designs GeneSys:用于GHz VLSI设计的叶细胞布局合成系统

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745196

B. Basaran, K. Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, S. Rangarajan, Naresh Sehgal

引用次数: 2

Formal system design based on the synchrony hypothesis, functional models, and skeletons 基于同步假设、功能模型和框架的正式系统设计

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745170

I. Sander, A. Jantsch

{"title":"Formal system design based on the synchrony hypothesis, functional models, and skeletons","authors":"I. Sander, A. Jantsch","doi":"10.1109/ICVD.1999.745170","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745170","url":null,"abstract":"Formal approaches to HW and system design have not been generally adopted because designers often view the modelling concepts in these approaches as unsuitable for their problems. Moreover they are frequently on a too high abstraction level to allow for efficient synthesis with today's techniques. We address this problem with a modelling method, which is strictly formal and based on formal semantics, a pure functional language, and the synchrony hypothesis. But the use of skeletons in conjunction with a proper computational model allows to associate a direct hardware interpretation. In particular we use the synchrony hypothesis and a timed signal model to provide a high abstraction for communication at the system level. This facilitates efficient modelling and design space exploration at the functional level, because the designer is not concerned with complex communication mechanisms, and functionality can easily be moved from one block to another. To bridge the gap between an elegant and abstract functional model and the details of an implementation we use skeletons to encapsulate primitive structures, such as FSMs, buffers, computation units, etc. in a purely functional way.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"435 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132495149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

A new approach for CMOS op-amp synthesis 一种CMOS运算放大器合成的新方法

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745147

P. Mandal, V. Visvanathan

引用次数: 11

Interconnect optimization strategies for high-performance VLSI designs 高性能VLSI设计的互连优化策略

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745199

A. Kahng, S. Muddu, E. Sarto

{"title":"Interconnect optimization strategies for high-performance VLSI designs","authors":"A. Kahng, S. Muddu, E. Sarto","doi":"10.1109/ICVD.1999.745199","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745199","url":null,"abstract":"Interconnect tuning and repeater insertion are necessary to optimize interconnect delay, signal performance and integrity, and interconnect manufacturability and reliability. Repeater insertion in interconnects is an increasingly important element in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We address four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133843099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Interconnect simple, accurate and statistical models using on-chip measurements for calibration 互连简单，准确和统计模型使用芯片上的测量校准

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745135

A. Doganis, James C. Chen

引用次数: 2

Compact, ultra low power, programmable continuous-time filter banks for feedback cancellation in hearing aid 紧凑型，超低功耗，可编程连续时间滤波器组，用于助听器的反馈消除

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745124

Kavita Nair, R. Harjani

{"title":"Compact, ultra low power, programmable continuous-time filter banks for feedback cancellation in hearing aid","authors":"Kavita Nair, R. Harjani","doi":"10.1109/ICVD.1999.745124","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745124","url":null,"abstract":"This paper describes the design of a compact, ultra low power continuous time programmable filter. Compact programmable filters are required for a number of applications. A particular application is in feedback cancellation filters in hearing aids. Here, a feedback cancellation filter that matches the open loop transfer function is used to suppress acoustic oscillations. Because of the complexity of the transfer function the number of poles in the cancellation filter is fairly large. To realize an integrated cancellation filter an ultra-low power transconductance cell with large linear range has been designed. Both measurement and simulation results are presented to confirm our design. The power consumption for a transconductance cell is comparable to the theoretical minimum bound and is measured to be 0.8 /spl mu/W at a 3 V supply. The linear input range for this cell is 2 V/sub p-p/. In this paper we also compare our design with a programmable switched capacitor implementation and show that there is a significant savings in area as well. The complete filter has been designed, implemented and fabricated in an 2 /spl mu/ CMOS technology.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Lossy compression of images using logic minimization 使用逻辑最小化的有损压缩图像

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745210

J. Augustine, W. Lynch, Yuke Wang, A. Al-Khalili

引用次数: 3

Functional decomposition through structural analysis of decision diagrams-the binary and multiple-valued cases 通过决策图的结构分析进行功能分解——二元和多值情况

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745151

L. Macchiarulo, P. Civera

引用次数: 2

Processor modeling for hardware software codesign 硬件软件协同设计的处理器建模

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745137

V. Rajesh, R. Moona

引用次数: 61

Efficient DC analysis of RVJ circuits for moment and derivative computations of interconnect networks RVJ电路的高效直流分析，用于互连网络的力矩和导数计算

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745144

S. Batterywala, H. Narayanan

引用次数: 11