Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)最新文献

Sub-circuit analysis for power supply rejection ratio in regulated cascode operational transconductance amplifiers and filters 稳压级联码运算跨导放大器和滤波器电源抑制比的子电路分析

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745143

A. Bhattacharyya, Saudas Dey

{"title":"Sub-circuit analysis for power supply rejection ratio in regulated cascode operational transconductance amplifiers and filters","authors":"A. Bhattacharyya, Saudas Dey","doi":"10.1109/ICVD.1999.745143","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745143","url":null,"abstract":"Operational Transconductance Amplifiers (OTA) form an integral part of OTA-C filters. The authors have experimented with OTA-C filters for frequency shaping purposes in micropower all-CMOS hearing aids as against conventionally used switched capacitor filters, as switched capacitor filters present problem due to switching noise and require a double polysilicon technology in a low voltage process. The power supply rejection ratio (PSRR) of such filters becomes important in hearing aids, as the negative supply voltage for the OTA is derived from the low voltage battery by the use of a dc to dc converter through capacitor switching where a ripple voltage on supply rail is inherent due to charging and discharging mechanism in the converter circuit. A regulated cascode (RGC) differential stage is used for OTA to increase the linearity of the differential input stage and ensure an acceptable level of CMRR. An important finding that has emerged in the present investigation from the viewpoint of application of OTA-C filters in hearing aids is that PSRR of high pass filter is much higher compared to that in low pass configuration. The results have been validated both by SPICE simulation and measurement of OTA-C filter chips fabricated for hearing aid application.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126192451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A complete characterization of path delay faults through stuck-at faults 通过卡滞故障完整表征路径延迟故障

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745203

S. Majumder, B. Bhattacharya, V. Agrawal, M. Bushnell

{"title":"A complete characterization of path delay faults through stuck-at faults","authors":"S. Majumder, B. Bhattacharya, V. Agrawal, M. Bushnell","doi":"10.1109/ICVD.1999.745203","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745203","url":null,"abstract":"A complete one-to-one characterization of path delay fault testability for a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent unfolded circuit. The unfolded circuit is obtained simply by replicating the cone feeding each internal fanout stem line, thereby making it internally fanout free. Unfolding preserves both functional, and structural characteristics of the original circuit. Earlier results describing correlation of path delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. We show that a path delay fault (rising or falling) is testable if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path delay faults related to testability under various classification schemes are interpreted using the stuck-at fault model alone in the unfolded circuit. The results unify most of the existing concepts, provide a better understanding of path delay faults in logic circuits, and have potential applications in identification of false paths.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122385245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Improved effective capacitance computations for use in logic and layout optimization 改进了用于逻辑和布局优化的有效电容计算

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745217

A. Kahng, S. Muddu

引用次数: 32

Component characterization and constraint transformation based on directed intervals for analog synthesis 模拟合成中基于有向区间的分量表征与约束变换

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745219

N. Dhanwada, A. Núñez-Aldana, R. Vemuri

引用次数: 11

Design and test of MEMS MEMS的设计与测试

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745160

B. Courtois, J. Karam, S. Mir, M. Lubaszewski, V. Székely, M. Rencz, K. Hofmann, M. Glesner

引用次数: 5

The retiming of single-phase clocked circuits containing level-sensitive latches 包含电平敏感锁存器的单相时钟电路的重新定时

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745189

Prashant Saxena, P. Pan, C. Liu

引用次数: 1

A low-power digital camera-on-a-chip implemented in CMOS active pixel approach 一种采用CMOS有源像素方法实现的低功耗单片数码相机

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745119

B. Pain, Guang Yang, B. Olson, T. Shaw, M. Ortiz, J. Heynssens, C. Wrigley, Charlie Ho

引用次数: 13

Exploiting isomorphism for compaction and faster simulation of binary decision diagrams 利用同构压缩和更快地模拟二进制决策图

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745173

P. Chauhan, P. Dasgupta, P. Chakrabarti

引用次数: 2

Improving area efficiency of residue number system based implementation of DSP algorithms 基于DSP算法的实现提高了残数系统的面积效率

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745179

M. Mahesh, Satrajit Gupta, M. Mehendale

引用次数: 1

Spec-based repeater insertion and wire sizing for on-chip interconnect 基于规范的中继器插入和片上互连的线尺寸

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745201

N. Menezes, C. C. Chen

{"title":"Spec-based repeater insertion and wire sizing for on-chip interconnect","authors":"N. Menezes, C. C. Chen","doi":"10.1109/ICVD.1999.745201","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745201","url":null,"abstract":"Recently Lillis, et al. (see Proc. Custom Integrated Conf., p. 259-262, May 1995) presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks. More importantly, Elmore delay techniques because of their inherent inaccuracy are not suited to spec-based design which is directed towards synthesizing nets with user-specified delay/transition time requirements at the sinks. In this paper we present techniques for delay and transition time optimization for RC nets in the context of accurate moment-matching techniques for computing the RC delays and transition times, and an accurate driver/repeater delay model. The asymptotic increase in runtime over the Elmore delay model is O(q/sup 2/) where q is the order of the moment-matching approximation. Experiments on industrial nets indicate that this increase in runtime is acceptable. Our algorithm yields delay and transition time estimates within 5% of circuit simulation results.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124383862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19