包含电平敏感锁存器的单相时钟电路的重新定时

Prashant Saxena, P. Pan, C. Liu
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引用次数: 1

摘要

以前基于锁存器的电路重新计时的方法使用了时钟的不同阶段来防止竞争条件。然而,这种方法不适用于单相时钟电路。因此,没有实用的公式来优化包含锁存器的单相时钟电路。我们提出了一种新的用于此类电路重定时的ILP公式,以及生成其约束集的有效算法。该公式可用于优化质量取决于闩锁位置的任何准则,并可表示为线性目标函数。作为例子,我们讨论了时钟周期和锁存器计数的优化。对于后者,我们描述了一个图变换来线性化基于最大值的目标函数。我们的实验表明,我们的配方是有效的,并产生了易于解决的ilp。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The retiming of single-phase clocked circuits containing level-sensitive latches
Previous approaches to the retiming of latch-based circuits have used the different phases of the clock to prevent race conditions. However, such an approach is not applicable to single-phase clocked circuits. Consequently there is no practical formulation that retimes single-phase clocked circuits containing latches optimally. We present a novel ILP formulation for the retiming of such circuits, along with efficient algorithms to generate its constraint set. This formulation can be used to optimize any criterion whose quality depends on the latch positions and that can be expressed as a linear objective function. As examples, we discuss the optimization of the clock period and the latch count. For the latter we describe a graph transformation to linearize the max-based objective function. Our experiments demonstrate that our formulation is efficient and generates ILPs that are easy to solve.
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