Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)最新文献_第8页

Near-optimum hierarchical layout synthesis of two-dimensional CMOS cells 二维CMOS电池的近最优分层布局合成

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745197

Avaneendra Gupta, J. Hayes

引用次数: 4

Recent advances in BDD based representations for Boolean functions: a survey 基于BDD的布尔函数表示的最新进展:综述

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745190

Amit Narayan

引用次数: 1

Exact output response computation of RC interconnects under polynomial input waveforms 多项式输入波形下RC互连的精确输出响应计算

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745142

Satrajit Gupta, L. Patnaik

引用次数: 3

Simulation and modeling of a multicast ATM switch 多播ATM交换机的仿真与建模

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745155

Ajoy C. Siddabathuni, M. Balakrishnan

引用次数: 0

Energy efficient datapath synthesis using dynamic frequency clocking and multiple voltages 使用动态频率时钟和多个电压的高能效数据路径合成

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745195

V. Krishna, N. Ranganathan, N. Vijaykrishnan

{"title":"Energy efficient datapath synthesis using dynamic frequency clocking and multiple voltages","authors":"V. Krishna, N. Ranganathan, N. Vijaykrishnan","doi":"10.1109/ICVD.1999.745195","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745195","url":null,"abstract":"In this paper, we propose an energy efficient synthesis technique for datapath circuits. Specifically, we propose a time and resource constrained scheduling algorithm, (DFMVS), which utilizes the concept of Dynamic Frequency Clocking and Multiple Voltage Scaling. In the dynamic frequency scheme, all units are driven by a single clock line which changes at run time depending on the functional unit active at that time. Recently, the use of multiple voltages has been investigated in the context of energy minimization. DFMVS consists of two modules: Dynamic-freq-sched and Modify-sched. Based on the dynamic frequency scheme, Dynamic-freq-sched generates an initial schedule in which the control steps are clocked at different frequencies. Modify-sched incorporates a schedule modifier, that regroups the operations of the initial schedule such that multiple voltages can be used to reduce the energy consumption. The algorithm has been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that using three supply saving of 53.5% (with the time constraint of 2.0 times the critical path) is obtained as compared to using a uni-frequency clocking scheme with a single supply voltage.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125327439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

A VLSI architecture for on-line image decompression using GF(2/sup 8/) cellular automata 基于GF(2/sup 8/)元胞自动机的图像在线解压缩VLSI结构

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745209

K. Paul, P. Dutta, D. R. Chowdhury, P. Nandi, P. P. Chaudhuri

引用次数: 0

A new test compression scheme 一种新的试验压缩方案

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745131

B. Bhaumik, G. Visweswaran, R. Lakshminarasimhan

引用次数: 0

A three-tier assertion technique for SPICE verification of transistor level timing analysis 用于晶体管级时序分析的SPICE验证的三层断言技术

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745145

S. Sundareswaran, D. Blaauw, A. Dharchoudhury

{"title":"A three-tier assertion technique for SPICE verification of transistor level timing analysis","authors":"S. Sundareswaran, D. Blaauw, A. Dharchoudhury","doi":"10.1109/ICVD.1999.745145","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745145","url":null,"abstract":"Static transistor level timing analysis has become a more and more accepted method for performance evaluation because of its reduced design cycle time when compared to the vector based timing analysis. These static timing analysis tools use transistor level delay modelling to identify timing-critical paths and estimate performance of the design. With increase in complexity of designs it becomes necessary to verify the timing-critical paths using SPICE-simulations. In order to perform accurate modelling for SPICE simulations, it becomes imperative to identify all the devices and the signal-states on the nodes, for a given input to output transition. The current techniques use greedy approaches for each input to output transition in a channel connected component. These techniques consider turning-on all transistors on the primary conducting path and turning-off remaining transistors on the side-paths. Thus, these techniques don't consider appropriate loading on the output node due to transistors on the side-paths and the fanout paths. These techniques also don't consider the input signal correlations. This paper presents a three-tier heuristics to determine side path assertions, such that it maximizes, as much as possible, the load at the output node, for a given set of input to output transitions. Also, a method to perform the fanout path assertions is presented. This technique has been used for SPICE-verification of the timing-critical paths of transistor level designs. The results have been compared using SPICE simulations of the same designs.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123138360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Characterizing individual gate power sensitivity in low power design 低功耗设计中单个栅极功率灵敏度的表征

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745275

U. Narayanan, G. Stamoulis, R. Roy

引用次数: 5

New and exact filling algorithms for layout density control 新的和精确的填充算法布局密度控制

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745133

A. Kahng, G. Robins, Anish Singh, A. Zelikovsky

引用次数: 26