Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)最新文献_第7页

Design for manufacturing in the semiconductor industry: the Litho/Design Workshops 半导体工业的制造设计:光刻/设计工作坊

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745134

F. Schellenberg

引用次数: 18

A state assignment scheme targeting performance and area 以性能和区域为目标的状态分配方案

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745185

B. Gupta, H. Narayanan, M. Desai

引用次数: 19

A semi-digital delay locked loop for clock skew minimization 一个半数字延迟锁定环时钟倾斜最小化

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745218

Joonbae Park, Y. Koo, Wonchan Kim

引用次数: 5

Low power code generation of multiplication-free linear transforms 无乘法线性变换的低功耗代码生成

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745122

M. Mehendale, S. Sherlekar

引用次数: 1

Automatic insertion of gated clocks at register transfer level 自动插入门控时钟在寄存器传输水平

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745123

N. Raghavan, V. Akella, Smita Bakshi

引用次数: 44

POWERTEST: a tool for energy conscious weighted random pattern testing POWERTEST:一个能源意识加权随机模式测试工具

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745191

Xiaodong Zhang, K. Roy, S. Bhawmik

{"title":"POWERTEST: a tool for energy conscious weighted random pattern testing","authors":"Xiaodong Zhang, K. Roy, S. Bhawmik","doi":"10.1109/ICVD.1999.745191","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745191","url":null,"abstract":"Due to the increasing use of portable computing and wireless communications systems, energy consumption is of major concern in today's VLSI circuits. With that in mind we present an energy conscious weighted random pattern testing technique for Built-In-Self-Test (BIST) applications. Energy consumption during BIST operation can be minimized while achieving high fault coverage. Simple measures of observability and controllability of circuit nodes are proposed based on primary input signal probability (probability that a signal is logic ONE). Such measures help determine the testability of a circuit. We developed a tool, POWERTEST, which uses a genetic algorithm based search to determine optimal weight sets (signal probabilities or input signal distribution) at primary inputs to minimize energy dissipations. The inputs conforming to the primary input weight set can be generated using cellular automata or LFSR (Linear Feedback Shift Register). We observed that a single input distribution (or weights) may not be sufficient for some random-pattern resistant circuits, while multiple distributions consume larger area. As a trade-off, two distributions have been used in our analysis. Results on ISCAS benchmark circuits show that energy reduction of up to 97.82% can be achieved (compared to equi-probable random-pattern testing with identical fault coverage) while achieving high fault coverage.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125039616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 74

Study of correlation of testability aspects of RTL description and resulting structural implementations 研究RTL描述的可测试性方面与由此产生的结构实现的相关性

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745157

Pradip A. Thaker, M. Zaghloul, M. Amin

{"title":"Study of correlation of testability aspects of RTL description and resulting structural implementations","authors":"Pradip A. Thaker, M. Zaghloul, M. Amin","doi":"10.1109/ICVD.1999.745157","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745157","url":null,"abstract":"RTL-based high level design methodology suffers a major drawback in the area of testability analysis due to lack of effective RTL fault models. Testability of a design is considered structure dependent. Since the structure of a design changes drastically with every logic synthesis run, testability analysis is performed only after final logic synthesis and therefore findings of such effort are too late to be implemented in the design without a significant schedule impact. In this paper we analyze the testability relationship between the RT level design and different structural (gate level) implementations resulting from optimization driven logic synthesis runs. We empirically establish that the testability properties of structural implementations are derived from architectural descriptions at the RT level and therefore logic synthesis does not significantly impact them. Furthermore, various different structural implementations resulting from logic synthesis (with different optimization constraints) exhibit poor testability in the same RTL design space. The data presented in this paper provides a missing key ingredient towards successful RTL fault modeling. We also propose the use of preliminary gate level netlist for early analysis to estimate testability properties of the final implementation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Analytical expressions for power dissipation of macro-blocks in DSP architectures DSP体系结构中宏块功耗的解析表达式

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745182

S. Bobba, I. Hajj, Naresh R Shanbhag

引用次数: 19

A test generator for segment delay faults 段延迟故障的测试发生器

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745202

Keerthi Heragu, J. Patel, V. Agrawal

{"title":"A test generator for segment delay faults","authors":"Keerthi Heragu, J. Patel, V. Agrawal","doi":"10.1109/ICVD.1999.745202","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745202","url":null,"abstract":"We propose a simulation-based technique that uses a genetic algorithm (GA) to generate tests for delay faults on segments of any given length. At every line, we assume that an upper bound on the number of testable segment faults that originate there is known. Such a bound is efficiently computed by an implication-based technique. The fitness function for the GA is derived from an objective function that favors vectors which might detect a large number of faults. This is accomplished by a simulator used as a base engine, by dynamically identifying a line m with the highest upper bound for the number of segments on which faults can and are yet to be tested, and by ranking vectors according to their ability to target the simultaneous objectives of invoking a transition on m and maximizing the number of signals that propagate robustly in the fanout cone of m. Rather than limiting the number of generations of evolution in the GA, we obtain improved results by using the diversity of the individuals in a population as a stopping criterion. Results indicate that for small segment lengths, reasonable robust segment delay test coverages can be obtained for most benchmark circuits. Also, the tests generated using the segment delay fault model detect a large number of transition and path delay faults. For example in the benchmark circuit c3540, tests generated for faults on segments of length 5 had a transition fault coverage of 96.1% and were able to detect 9,246 path faults.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Formal verification of a snoop-based cache coherence protocol using symbolic model checking 使用符号模型检查的基于窥探的缓存一致性协议的形式化验证

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745162

Srivatsan Srinivasan, Parminder Chhabra, P. Jaini, A. Aziz, L. John

引用次数: 9