Low power code generation of multiplication-free linear transforms

Abstract

The paper presents low power code generation of multiplication-free linear transforms targeted to both the register-rich RISC architectures and the single-register accumulator based DSP architectures. For register rich architectures, we present ordered chain-type DAC as the optimum structure for low power code generation of 1-dimensional transforms. For 2-dimensional transforms, we present an algorithm that performs instruction scheduling followed by register assignment for low power. For single-register architectures, we present a node re-ordering technique for reducing power dissipation. We present results to highlight the effectiveness of these techniques.