Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)最新文献_第5页

Heuristic technology mapper for LUT based FPGAs 基于LUT的fpga启发式技术映射器

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745187

Chitrasena Bhat, N. Chiplunkar

引用次数: 0

Efficient techniques for reducing IDDQ observation time for sequential circuits 减少顺序电路IDDQ观测时间的有效技术

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745127

Y. Higami, K. Saluja, K. Kinoshita

引用次数: 6

A low cost approach for detecting, locating, and avoiding interconnect faults in FPGA-based reconfigurable systems 在基于fpga的可重构系统中，一种低成本的互连故障检测、定位和避免方法

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745159

D. Das, N. Touba

引用次数: 61

FzCRITIC-a functional timing verifier using a novel fuzzy delay model fzcritical -一种基于新型模糊延迟模型的功能时序验证器

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745153

Rathish Jayabharathi, M. d'Abreu, J. Abraham

引用次数: 4

Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation 以最小功耗为目标的不完全指定模式序列的赋值与重排序

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745121

P. Flores, José C. Costa, H. Neto, J. Monteiro, Joao Marques-Silva

引用次数: 55

Sequential multi-valued network simplification using redundancy removal 基于冗余去除的顺序多值网络简化

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745149

S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli

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引用次数: 3

Simultaneous scheduling, binding and floorplanning for interconnect power optimization 同时调度，绑定和平面规划互连电源优化

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745192

P. Prabhakaran, P. Banerjee, Jim E. Crenshaw, M. Sarrafzadeh

引用次数: 27

Empirical computation of reject ratio in VLSI testing 超大规模集成电路测试中拒绝率的经验计算

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745205

Shashank K. Mehta, S. Seth

引用次数: 0

Satisfiability-based detailed FPGA routing 基于可满足性的详细FPGA路由

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745216

Gi-Joon Nam, K. Sakallah, Rob A. Rutenbar

引用次数: 10

Multi-valued logic synthesis 多值逻辑综合

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013) Pub Date : 1999-01-10 DOI: 10.1109/ICVD.1999.745148

R. Brayton, S. Khatri

引用次数: 53